aboutsummaryrefslogtreecommitdiff
path: root/src/codegen.zig
AgeCommit message (Expand)Author
2021-05-01stage2: dbg_stmt ZIR instructions have line/colAndrew Kelley
2021-04-28stage2: implement semantic analysis for functions and global varsAndrew Kelley
2021-04-28stage2: semaDecl properly analyzes the decl blockAndrew Kelley
2021-04-28Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgenAndrew Kelley
2021-04-25stage2 register manager: Use an array instead of a hashmap for trackingjoachimschmidt557
2021-04-24Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgenAndrew Kelley
2021-04-20stage2: fix compile error in codegenjacob gw
2021-04-19AstGen: implement inline asm outputAndrew Kelley
2021-04-17stage2 codegen: Fix silent bug in reuseOperandjoachimschmidt557
2021-04-15stage2: entry point via std lib and proper updated file detectionAndrew Kelley
2021-04-11stage2 ARM: Add fibonacci testjoachimschmidt557
2021-04-11stage2 codegen: Set MCValue of register arguments to their stack copyjoachimschmidt557
2021-04-09Merge pull request #8470 from ziglang/stage2-startAndrew Kelley
2021-04-08stage2: simplify Decl src_node fieldAndrew Kelley
2021-04-08Merge pull request #8464 from gracefuu/grace/wasm-opsAndrew Kelley
2021-04-08stage2: Add .div to ir.ziggracefu
2021-04-07stage2 regalloc: Add unit test for getRegjoachimschmidt557
2021-04-06stage2 regalloc: Add getReg and getRegWithoutTrackingjoachimschmidt557
2021-04-02stage2 AArch64: Add ldrh and ldrb instructionsjoachimschmidt557
2021-04-02stage2 register_manager: Add unit tests for tryAllocReg and allocRegjoachimschmidt557
2021-04-02stage2 codegen: Extract register management code into separate filejoachimschmidt557
2021-04-01stage2: implement structs in the frontendAndrew Kelley
2021-03-31Merge pull request #8266 from ziglang/zir-memory-layoutAndrew Kelley
2021-03-31Sema: implement switch validation for rangesAndrew Kelley
2021-03-31stage2 codegen: Make sure function return value is in a calleejoachimschmidt557
2021-03-31stage2 AArch64: implement strb and strhjoachimschmidt557
2021-03-28stage2: implement sema for @errorToInt and @intToErrorjacob gw
2021-03-18stage2: codegen: update asm IR to new namesAndrew Kelley
2021-03-18stage2: the code is compiling againAndrew Kelley
2021-03-18stage2: get Module and Sema compiling againAndrew Kelley
2021-03-18Merge remote-tracking branch 'origin/master' into zir-memory-layoutAndrew Kelley
2021-03-17stage2: Module and Sema are compiling againAndrew Kelley
2021-03-17macho: offset table part of GOTJakub Konka
2021-03-17macho: apply some renames to bring closer to zldJakub Konka
2021-03-11Merge pull request #7934 from Vexu/stage2-cbeAndrew Kelley
2021-03-11stage2 tzir: Add wrapping integer arithmetic instructionsjoachimschmidt557
2021-03-08cbe: add error comparison supportjacob gw
2021-03-02stage2 ARM: Implement basic integer multiplicationjoachimschmidt557
2021-02-25improve stage2 to allow catch at comptime:g-w1
2021-02-25stage2 ARM: Save callee-saved registersjoachimschmidt557
2021-02-24zig fmt src/Andrew Kelley
2021-02-24Merge remote-tracking branch 'origin/master' into ast-memory-layoutAndrew Kelley
2021-02-21stage2 codegen: Add Type argument to genSetRegjoachimschmidt557
2021-02-12stage2: more progress towards Module/astgen building with new mem layoutAndrew Kelley
2021-02-12stage2: fix zero-sized function parameters (#7998)Tadeo Kondrak
2021-02-09require specifier for arrayish typesJonathan Marler
2021-02-09stage2 ARM: fix register allocation in genArmBinOpjoachimschmidt557
2021-02-01stage2 ARM: save function arguments to stack for debuggingjoachimschmidt557
2021-01-31astgen: rework labeled blocksAndrew Kelley
2021-01-31sema: after block gets peer type resolved, insert type coercionsAndrew Kelley
generated by cgit v1.2.3 (git 2.39.1) at 2025-12-28 04:51:42 +0000