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| author | joachimschmidt557 <joachim.schmidt557@outlook.com> | 2021-04-02 18:57:49 +0200 |
|---|---|---|
| committer | Andrew Kelley <andrew@ziglang.org> | 2021-04-02 14:46:30 -0700 |
| commit | 43d364afef7f0609f9d897c7ff129ba6b9b3cab0 (patch) | |
| tree | eb4cf7dc62230a55b03f166ffbecd8c463ef97e9 /src/codegen.zig | |
| parent | 12e25237309a0e358418e17ed1a71e123b89a7be (diff) | |
| download | zig-43d364afef7f0609f9d897c7ff129ba6b9b3cab0.tar.gz zig-43d364afef7f0609f9d897c7ff129ba6b9b3cab0.zip | |
stage2 AArch64: Add ldrh and ldrb instructions
Diffstat (limited to 'src/codegen.zig')
| -rw-r--r-- | src/codegen.zig | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/src/codegen.zig b/src/codegen.zig index beb3540d37..fbd412ceba 100644 --- a/src/codegen.zig +++ b/src/codegen.zig @@ -3302,6 +3302,43 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.ldr(reg, .{ .register = .{ .rn = reg } }).toU32()); } }, + .stack_offset => |unadjusted_off| { + // TODO: maybe addressing from sp instead of fp + const abi_size = ty.abiSize(self.target.*); + const adj_off = unadjusted_off + abi_size; + + const rn: Register = switch (arch) { + .aarch64, .aarch64_be => .x29, + .aarch64_32 => .w29, + else => unreachable, + }; + + const offset = if (math.cast(i9, adj_off)) |imm| + Instruction.LoadStoreOffset.imm_post_index(-imm) + else |_| + Instruction.LoadStoreOffset.reg(try self.copyToTmpRegister(src, Type.initTag(.u64), MCValue{ .immediate = adj_off })); + + switch (abi_size) { + 1, 2 => { + const ldr = switch (abi_size) { + 1 => Instruction.ldrb, + 2 => Instruction.ldrh, + else => unreachable, // unexpected abi size + }; + + writeInt(u32, try self.code.addManyAsArray(4), ldr(reg, rn, .{ + .offset = offset, + }).toU32()); + }, + 4, 8 => { + writeInt(u32, try self.code.addManyAsArray(4), Instruction.ldr(reg, .{ .register = .{ + .rn = rn, + .offset = offset, + } }).toU32()); + }, + else => return self.fail(src, "TODO implement genSetReg other types abi_size={}", .{abi_size}), + } + }, else => return self.fail(src, "TODO implement genSetReg for aarch64 {}", .{mcv}), }, .riscv64 => switch (mcv) { |