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2021-01-17stage2 aarch64: add basic genSetStackJakub Konka
2021-01-16stage2: implement error notes and regress -femit-zirAndrew Kelley
* Implement error notes - note: other symbol exported here - note: previous else prong is here - note: previous '_' prong is here * Add Compilation.CObject.ErrorMsg. This object properly converts to AllErrors.Message when the time comes. * Add Compilation.CObject.failure_retryable. Properly handles out-of-memory and other transient failures. * Introduce Module.SrcLoc which has not only a byte offset but also references the file which the byte offset applies to. * Scope.Block now contains both a pointer to the "owner" Decl and the "source" Decl. As an example, during inline function call, the "owner" will be the Decl of the caller and the "source" will be the Decl of the callee. * Module.ErrorMsg now sports a `file_scope` field so that notes can refer to source locations in a file other than the parent error message. * Some instances where a `*Scope` was stored, now store a `*Scope.Container`. * Some methods in the `Scope` namespace were moved to the more specific type, since there was only an implementation for one particular tag. - `removeDecl` moved to `Scope.Container` - `destroy` moved to `Scope.File` * Two kinds of Scope deleted: - zir_module - decl * astgen: properly use DeclVal / DeclRef. DeclVal was incorrectly changed to be a reference; this commit fixes it. Fewer ZIR instructions processed as a result. - declval_in_module is renamed to declval - previous declval ZIR instruction is deleted; it was only for .zir files. * Test harness: friendlier diagnostics when an unexpected set of errors is encountered. * zir_sema: fix analyzeInstBlockFlat by properly calling resolvingInst on the last zir instruction in the block. Compile log implementation: * Write to a buffer rather than directly to stderr. * Only keep track of 1 callsite per Decl. * No longer mutate the ZIR Inst struct data. * "Compile log statement found" errors are only emitted when there are no other compile errors. -femit-zir and support for .zir source files is regressed. If we wanted to support this again, outputting .zir would need to be done as yet another backend rather than in the haphazard way it was previously implemented. For parsing .zir, it was implemented previously in a way that was not helpful for debugging. We need tighter integration with the test harness for it to be useful; so clearly a rewrite is needed. Given that a rewrite is needed, and it was getting in the way of progress and organization of the rest of stage2, I regressed the feature.
2021-01-16stage2 ARM: add extra load/store instructionsjoachimschmidt557
2021-01-16stage2 AArch64: add very basic return valuesjoachimschmidt557
2021-01-13macho: add x86_64 supportJakub Konka
2021-01-13macho: document more code + add test caseJakub Konka
2021-01-13macho: refactor writing and managing externsJakub Konka
2021-01-13macho: write out stubs for new externs onlyJakub Konka
2021-01-13macho: populate stubs and stub_helperJakub Konka
2021-01-13stage2: lay the groundwork in prep for extern fnJakub Konka
This commit lays the groundwork in preparation for implementing handling of extern functions in various backends.
2021-01-10stage2: fix bug in genArgjoachimschmidt557
When an argument is unused in the function body, still increment arg_index so we still select the correct arguments in the args slice.
2021-01-06Merge pull request #7622 from tetsuo-cpp/array-hash-map-improvementsAndrew Kelley
std: Support equivalent ArrayList operations in ArrayHashMap
2021-01-06stage2 ARM: fix stack offsets for genSetReg and genSetStackjoachimschmidt557
2021-01-06stage2 ARM: fix offsets in exitlude jump relocationsjoachimschmidt557
2021-01-06std: Support equivalent ArrayList operations in ArrayHashMapAlex Cameron
2021-01-03stage2 x86_64: fix bug in Function.genjoachimschmidt557
Previously, the x86_64 backend would remove code for exitlude relocs if the jump amount were 0. This causes issues as earlier jumps rely on the jump being present at the same address.
2021-01-03stage2: implement basic function params aarch64Jakub Konka
Implement missing `.register` prong for `aarch64` `genSetReg`.
2021-01-02stage2: re-use ZIR for comptime and inline callsAndrew Kelley
Instead of freeing ZIR after semantic analysis, we keep it around so that it can be used for comptime calls, inline calls, and generic function calls. ZIR memory is now managed by the Decl arena. Debug dump() functions are conditionally compiled; only available in Debug builds of the compiler. Add a test for an inline function call.
2021-01-02stage2: implement function call inlining in the frontendAndrew Kelley
* remove the -Ddump-zir thing. that's handled through --verbose-ir * rework Fn to have an is_inline flag without requiring any more memory on the heap per function. * implement a rough first version of dumping typed zir (tzir) which is a lot more helpful for debugging than what we had before. We don't have a way to parse it though. * keep track of whether the inline-ness of a function changes because if it does we have to go update callsites. * add compile error for inline and export used together. inline function calls and comptime function calls are implemented the same way. A block instruction is set up to capture the result, and then a scope is set up that has a flag for is_comptime and some state if the scope is being inlined. when analyzing `ret` instructions, zig looks for inlining state in the scope, and if found, treats `ret` as a `break` instruction instead, with the target block being the one set up at the inline callsite. Follow-up items: * Complete out the debug TZIR dumping code. * Don't redundantly generate ZIR for each inline/comptime function call. Instead we should add a new state enum tag to Fn. * comptime and inlining branch quotas. * Add more test cases.
2021-01-02stage2: Use {s} instead of {} when formatting stringsLemonBoy
2021-01-01stage2 AArch64: add logical (shifted register) instructionsjoachimschmidt557
2021-01-01stage2 ARM: implement genSetReg with compare_flagsjoachimschmidt557
2021-01-01stage2 ARM: implement genCondBr for compare_flagsjoachimschmidt557
2021-01-01stage2 ARM: implement genCondBrjoachimschmidt557
2020-12-30stage2: rework Value Payload layoutAndrew Kelley
This is the same as the previous commit but for Value instead of Type. Add `Value.castTag` and note that it is preferable to call than `Value.cast`. This matches other abstractions in the codebase. Added a convenience function `Value.Tag.create` which really cleans up the callsites of creating `Value` objects. `Value` tags can now share payload types. This is in preparation for another improvement that I want to do.
2020-12-30stage2: rework Type Payload layoutAndrew Kelley
Add `Type.castTag` and note that it is preferable to call than `Type.cast`. This matches other abstractions in the codebase. Added a convenience function `Type.Tag.create` which really cleans up the callsites of creating `Type` objects. `Type` payloads can now share types. This is in preparation for another improvement that I want to do.
2020-12-21stage2 ARM: implement basic binary bitwise operationsjoachimschmidt557
2020-12-09stage2+aarch64: clean up offset helper structsJakub Konka
2020-12-09stage2+aarch64: fix stage2 testsJakub Konka
2020-12-09stage2+aarch64: use stp and ldp to navigate MachO jump tableJakub Konka
2020-12-03Merge pull request #7273 from kubkon/lld-codesig-pocAndrew Kelley
lld+macho: patch lld output on Apple Silicon by calculating and embedding adhoc code signature
2020-12-02stage2: wire up -Dskip-non-nativeAndrew Kelley
The purpose of this is to save time in the edit-compile-test cycle when working on stage2 code.
2020-12-01lld: use commands.LoadCommand in self-hosted linkerJakub Konka
2020-11-28stage2 ARM: use strb + implement genBoolOpjoachimschmidt557
2020-11-28stage2 ARM: Implement genNotjoachimschmidt557
2020-11-28stage2 codegen: use switch in genBoolOpjoachimschmidt557
2020-11-28stage2 ARM: genAdd, genSub for simple casesjoachimschmidt557
2020-11-27stage2 macho: apply more review commentsJakub Konka
2020-11-27Update src/codegen.zigJakub Konka
Co-authored-by: Andrew Kelley <andrew@ziglang.org>
2020-11-26stage2 macho: move PIE fixups to link file; fix testsJakub Konka
2020-11-26stage2 macho: add orr and orn instructionsJakub Konka
2020-11-26stage2 macho: Hello, Silicon!Jakub Konka
2020-11-26stage2 macho: refactor PIE generation on x86_64Jakub Konka
2020-11-26stage2 macho: first, rough draft at trampoliningJakub Konka
2020-11-26stage2 macho: use RIP-relative for memory-set regs x86_64Jakub Konka
2020-11-19Add builtin.Signedness, use it instead of is_signedTadeo Kondrak
2020-11-16Move leb128 and remove trivial *mem functions as discussed in #5588 (#6876)tgschultz
* Move leb128 out of debug and remove trivial *mem functions as discussed in #5588 * Turns out one of the *Mem functions was used by MachO. Replaced with trivial use of FixedBufferStream.
2020-11-11stage2 aarch64: add genCall for aarch64 MachOJakub Konka
2020-11-11stage2 aarch64: add .memory prong in genSetRegJakub Konka
2020-11-11stage2 ARM: start implementing genCall for ELF + genSetReg immediatesjoachimschmidt557