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AgeCommit message (Expand)Author
2021-05-14stage2 register manager: clean up API and add more unit testsjoachimschmidt557
2021-05-09stage2 ARM: Overhaul of genArmBinOpjoachimschmidt557
2021-05-09Merge pull request #8474 from gracefuu/grace/encode-instructionAndrew Kelley
2021-04-25stage2 register manager: Use an array instead of a hashmap for trackingjoachimschmidt557
2021-04-17stage2 codegen: Fix silent bug in reuseOperandjoachimschmidt557
2021-04-16stage2 x86_64: fix incorrect comment in genX8664BinMathgracefu
2021-04-16stage2 x86_64: force 64 bit mode when loading address of GOTgracefu
2021-04-16stage2 x86_64: fix codegen ensureCapacity bug for function callsgracefu
2021-04-16stage2 x86_64: bugfix abi_size == 64 should be abi_size == 8gracefu
2021-04-16stage2 x86_64: try to fix RIP-relative offset to GOT for machogracefu
2021-04-16stage2 x86_64: simplify inst encoder to a set of dumb helper fnsgracefu
2021-04-16stage2 x86_64: implement integer mulgracefu
2021-04-16stage2 x86_64: use abi size to determine 64-bit operationgracefu
2021-04-16stage2 x86_64: refactor codegen to use inst encodergracefu
2021-04-11stage2 ARM: Add fibonacci testjoachimschmidt557
2021-04-11stage2 codegen: Set MCValue of register arguments to their stack copyjoachimschmidt557
2021-04-09Merge pull request #8470 from ziglang/stage2-startAndrew Kelley
2021-04-08stage2: simplify Decl src_node fieldAndrew Kelley
2021-04-08Merge pull request #8464 from gracefuu/grace/wasm-opsAndrew Kelley
2021-04-08stage2: Add .div to ir.ziggracefu
2021-04-07stage2 regalloc: Add unit test for getRegjoachimschmidt557
2021-04-06stage2 regalloc: Add getReg and getRegWithoutTrackingjoachimschmidt557
2021-04-02stage2 AArch64: Add ldrh and ldrb instructionsjoachimschmidt557
2021-04-02stage2 register_manager: Add unit tests for tryAllocReg and allocRegjoachimschmidt557
2021-04-02stage2 codegen: Extract register management code into separate filejoachimschmidt557
2021-04-01stage2: implement structs in the frontendAndrew Kelley
2021-03-31Merge pull request #8266 from ziglang/zir-memory-layoutAndrew Kelley
2021-03-31Sema: implement switch validation for rangesAndrew Kelley
2021-03-31stage2 codegen: Make sure function return value is in a calleejoachimschmidt557
2021-03-31stage2 AArch64: implement strb and strhjoachimschmidt557
2021-03-28stage2: implement sema for @errorToInt and @intToErrorjacob gw
2021-03-18stage2: codegen: update asm IR to new namesAndrew Kelley
2021-03-18stage2: the code is compiling againAndrew Kelley
2021-03-18stage2: get Module and Sema compiling againAndrew Kelley
2021-03-18Merge remote-tracking branch 'origin/master' into zir-memory-layoutAndrew Kelley
2021-03-17stage2: Module and Sema are compiling againAndrew Kelley
2021-03-17macho: offset table part of GOTJakub Konka
2021-03-17macho: apply some renames to bring closer to zldJakub Konka
2021-03-11Merge pull request #7934 from Vexu/stage2-cbeAndrew Kelley
2021-03-11stage2 tzir: Add wrapping integer arithmetic instructionsjoachimschmidt557
2021-03-08cbe: add error comparison supportjacob gw
2021-03-02stage2 ARM: Implement basic integer multiplicationjoachimschmidt557
2021-02-25improve stage2 to allow catch at comptime:g-w1
2021-02-25stage2 ARM: Save callee-saved registersjoachimschmidt557
2021-02-24zig fmt src/Andrew Kelley
2021-02-24Merge remote-tracking branch 'origin/master' into ast-memory-layoutAndrew Kelley
2021-02-21stage2 codegen: Add Type argument to genSetRegjoachimschmidt557
2021-02-12stage2: more progress towards Module/astgen building with new mem layoutAndrew Kelley
2021-02-12stage2: fix zero-sized function parameters (#7998)Tadeo Kondrak
2021-02-09require specifier for arrayish typesJonathan Marler
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