| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2025-07-02 | compiler: delete aarch64 backend | Andrew Kelley | |
| this backend was abandoned before it was completed, and it is not worth salvaging. | |||
| 2025-06-12 | x86_64: remove air references from mir | Jacob Young | |
| 2025-06-12 | compiler: get most backends compiling again | mlugg | |
| As of this commit, every backend other than self-hosted Wasm and self-hosted SPIR-V compiles and (at least somewhat) functions again. Those two backends are currently disabled with panics. Note that `Zcu.Feature.separate_thread` is *not* enabled for the fixed backends. Avoiding linker references from codegen is a non-trivial task, and can be done after this branch. | |||
| 2024-10-10 | arch/aarch64/Mir: fix spelling (pseudo instead of psuedo) | Samuel Fiedler | |
| 2024-03-01 | compiler: audit debug mode checks | Jacob Young | |
| * Introduce `-Ddebug-extensions` for enabling compiler debug helpers * Replace safety mode checks with `std.debug.runtime_safety` * Replace debugger helper checks with `!builtin.strip_debug_info` Sometimes, you just have to debug optimized compilers... | |||
| 2023-06-24 | all: migrate code to new cast builtin syntax | mlugg | |
| Most of this migration was performed automatically with `zig fmt`. There were a few exceptions which I had to manually fix: * `@alignCast` and `@addrSpaceCast` cannot be automatically rewritten * `@truncate`'s fixup is incorrect for vectors * Test cases are not formatted, and their error locations change | |||
| 2022-12-17 | std.builtin: rename Type.UnionField and Type.StructField's field_type to type | r00ster91 | |
| 2022-11-05 | coff: compile and link simple exit program on arm64 | Jakub Konka | |
| * make image base target dependent * fix relocs to imports | |||
| 2022-11-01 | stage2 AArch64: implement min/max | joachimschmidt557 | |
| 2022-10-20 | stage2 AArch64: introduce ldr_ptr_stack Mir instruction | joachimschmidt557 | |
| 2022-10-20 | stage2 AArch64: simplify allocMem | joachimschmidt557 | |
| 2022-09-13 | stage2: support being built in ReleaseSafe mode | Andrew Kelley | |
| 2022-08-05 | stage2 AArch64: implement basic integer rem/mod | joachimschmidt557 | |
| 2022-08-05 | stage2 AArch64: implement basic integer division | joachimschmidt557 | |
| 2022-08-05 | stage2 AArch64: all arguments passed via stack from now on | joachimschmidt557 | |
| Only in the Undefined calling convention, not in other calling conventions | |||
| 2022-08-05 | stage2 AArch64: introduce MCValue.stack_argument_offset | joachimschmidt557 | |
| This new MCValue union member shares the same semantics as the MCValue type of the same name in the ARM backend. | |||
| 2022-07-22 | macho: improve logs for dyld info | Jakub Konka | |
| 2022-07-22 | macho: rework symbol handling to match zld/ELF | Jakub Konka | |
| Now, each object file will store a mutable table of symbols that it defines. Upon symbol resolution between object files, the symbol will be updated with a globally allocated section ordinal and address in virtual memory. If the object defines a globally available symbol, its location only (comprising of the symbol index and object index) will be stored in the globals map for easy access when relocating, etc. This approach cleans up the symbol management significantly, and matches the status quo used in zld/ELF. Additionally, this makes scoping symbol stabs easier too as they are now naturally contained within each object file. | |||
| 2022-05-05 | aarch64: fix mul_with_overflow for ints <= 32bits | Jakub Konka | |
| 2022-05-05 | aarch64: implement mul_with_overflow for ints in range 33-64 bits incl | Jakub Konka | |
| 2022-05-05 | aarch64: implement mul_with_overflow for <= 32bit ints | Jakub Konka | |
| Add emitters for `smull`, `umull` and `tst (immediate)` instructions. | |||
| 2022-05-05 | stage2 AArch64: implement {add,sub}_with_overflow for all ints < 64 | joachimschmidt557 | |
| 2022-04-19 | stage2 AArch64: Add ldrsb, ldrsh instructions | joachimschmidt557 | |
| 2022-04-19 | stage2 AArch64: Implement basic truncate functionality | joachimschmidt557 | |
| 2022-03-25 | stage2 AArch64: lower cmp to binOp | joachimschmidt557 | |
| 2022-03-13 | stage2 AArch64: Implement bit shifting with immediate operands | joachimschmidt557 | |
| 2022-03-13 | stage2 AArch64: implement bit shifts with register operands | joachimschmidt557 | |
| 2022-03-05 | stage2 AArch64: implement bitwise binary operations | joachimschmidt557 | |
| for integers with bit sizes <= 64 | |||
| 2022-03-05 | stage2 AArch64: introduce logical immediate instructions | joachimschmidt557 | |
| 2022-02-23 | stage2 AArch64: more support for MCValue.got_load and direct_load | joachimschmidt557 | |
| 2022-02-23 | stage2 AArch64: remove MIR load_memory instruction | joachimschmidt557 | |
| This instruction now just represents loading from a hard-coded adrress after extracting the other use cases for load_memory into load_got and load_direct. | |||
| 2022-02-15 | aarch64: introduce MCValue.got_load and MCValue.direct_load | Jakub Konka | |
| This matches the current design in x86_64 backend and significantly simplifies handling of PIE targets in aarch64 backend. | |||
| 2022-02-14 | stage2 AArch64: Implement not for booleans | joachimschmidt557 | |
| 2022-02-14 | stage2 AArch64: implement cond_br for other MCValues | joachimschmidt557 | |
| 2022-02-14 | stage2 AArch64: Implement binOp for add, sub | joachimschmidt557 | |
| 2022-02-14 | stage2 AArch64: minor refactors in Mir + Emit | joachimschmidt557 | |
| 2022-02-14 | stage2 AArch64: implement slice_len and slice_elem_val | joachimschmidt557 | |
| 2022-02-14 | stage2 AArch64: implement loading from register | joachimschmidt557 | |
| 2022-02-11 | macho: correctly lower slices incl reloc and rebase tracking | Jakub Konka | |
| Match changes required to `Elf` linker, which enable lowering of const slices on `MachO` targets. Expand `Mir` instructions requiring the knowledge of the containing atom - pass the symbol index into the linker's table from codegen via mir to emitter, to then utilise it in the linker. | |||
| 2022-01-14 | stage2 AArch64: split ldr/str into {ldr,str}_register and _immediate | joachimschmidt557 | |
| 2021-12-19 | stage2 AArch64: Implement saving callee-saved registers | joachimschmidt557 | |
| 2021-11-30 | allocgate: std Allocator interface refactor | Lee Cannon | |
| 2021-11-12 | stage2 AArch64: add new load/store from/to stack MIR instructions | joachimschmidt557 | |
| 2021-11-10 | stage2 AArch64: implement airCondBr | joachimschmidt557 | |
| 2021-11-10 | stage2 AArch64: implement genSetReg for condition flags | joachimschmidt557 | |
| 2021-11-10 | stage2 AArch64: implement airCmp | joachimschmidt557 | |
| 2021-10-31 | stage2 AArch64: implement emit debug line info | joachimschmidt557 | |
| 2021-10-31 | stage2 AArch64 Emit: implement call_extern and load_memory | joachimschmidt557 | |
| 2021-10-31 | stage2 AArch64: begin transition to MIR | joachimschmidt557 | |
| This commit includes the transitions for the following instructions: - add_immediate - b - bl - blr - brk - ldp - ldr - ldrb - ldrh - mov_to_from_sp - mov_register - movk - movz - nop - ret - stp - str - strb - strh - sub_immediate - svc | |||
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index : zig | |
| General-purpose programming language and toolchain for maintaining robust, optimal, and reusable software. https://ziglang.org |
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