stage2 AArch64: Implement basic truncate functionality

1 files changed, 31 insertions, 7 deletions

diff --git a/src/arch/aarch64/Mir.zig b/src/arch/aarch64/Mir.zig
index 6515a8da2e..dcde591a07 100644
--- a/src/arch/aarch64/Mir.zig
+++ b/src/arch/aarch64/Mir.zig
@@ -130,6 +130,14 @@ pub const Inst = struct {
         push_regs,
         /// Return from subroutine
         ret,
+        /// Signed bitfield extract
+        sbfx,
+        /// Signed extend byte
+        sxtb,
+        /// Signed extend halfword
+        sxth,
+        /// Signed extend word
+        sxtw,
         /// Store Pair of Registers
         stp,
         /// Pseudo-instruction: Store to stack
@@ -156,6 +164,12 @@ pub const Inst = struct {
         sub_shifted_register,
         /// Supervisor Call
         svc,
+        /// Unsigned bitfield extract
+        ubfx,
+        /// Unsigned extend byte
+        uxtb,
+        /// Unsigned extend halfword
+        uxth,
     };
 
     /// The position of an MIR instruction within the `Mir` instructions array.
@@ -225,13 +239,6 @@ pub const Inst = struct {
             rt: Register,
             inst: Index,
         },
-        /// Two registers
-        ///
-        /// Used by e.g. mov_register
-        rr: struct {
-            rd: Register,
-            rn: Register,
-        },
         /// A register, an unsigned 12-bit immediate, and an optional shift
         ///
         /// Used by e.g. cmp_immediate
@@ -240,6 +247,13 @@ pub const Inst = struct {
             imm12: u12,
             sh: u1 = 0,
         },
+        /// Two registers
+        ///
+        /// Used by e.g. mov_register
+        rr: struct {
+            rd: Register,
+            rn: Register,
+        },
         /// Two registers, an unsigned 12-bit immediate, and an optional shift
         ///
         /// Used by e.g. sub_immediate
@@ -268,6 +282,16 @@ pub const Inst = struct {
             imm6: u6,
             shift: bits.Instruction.LogicalShiftedRegisterShift,
         },
+        /// Two registers and a lsb (range 0-63) and a width (range
+        /// 1-64)
+        ///
+        /// Used by e.g. ubfx
+        rr_lsb_width: struct {
+            rd: Register,
+            rn: Register,
+            lsb: u6,
+            width: u7,
+        },
         /// Two registers and a bitmask immediate
         ///
         /// Used by e.g. eor_immediate