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path: root/src/arch/aarch64/CodeGen.zig
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2022-02-18stage2: Implement `@bitReverse` and `@byteSwap`Cody Tapscott
This change implements the above built-ins for Sema and the LLVM backend. Other backends have had placeholders added for lowering.
2022-02-16stage2 AArch64: Simplify and correct invocations of genInlineMemcpyjoachimschmidt557
Previously, the invocations used movk instead of movz
2022-02-15aarch64: add lowerUnnamedConst glue to codegenJakub Konka
2022-02-15aarch64: introduce MCValue.got_load and MCValue.direct_loadJakub Konka
This matches the current design in x86_64 backend and significantly simplifies handling of PIE targets in aarch64 backend.
2022-02-14stage2 AArch64: Enable behavior testingjoachimschmidt557
2022-02-14stage2 AArch64: Implement calling function pointersjoachimschmidt557
2022-02-14stage2 AArch64: Fix issue in binOp and add regression testjoachimschmidt557
2022-02-14stage2 AArch64: Implement not for booleansjoachimschmidt557
2022-02-14stage2 AArch64: implement cond_br for other MCValuesjoachimschmidt557
2022-02-14stage2 AArch64: Implement binOp for add, subjoachimschmidt557
2022-02-14stage2 AArch64: extract store out of airStore for recursive callsjoachimschmidt557
2022-02-14stage2 AArch64: minor refactors in Mir + Emitjoachimschmidt557
2022-02-14stage2 AArch64: implement unwrap_errunion_err and struct_field_ptrjoachimschmidt557
2022-02-14stage2 AArch64: implement slice_len and slice_elem_valjoachimschmidt557
2022-02-14stage2 AArch64: implement loading from registerjoachimschmidt557
2022-02-14stage2 AArch64: implement is_err/is_non_err for simple error unionsjoachimschmidt557
2022-02-11macho: correctly lower slices incl reloc and rebase trackingJakub Konka
Match changes required to `Elf` linker, which enable lowering of const slices on `MachO` targets. Expand `Mir` instructions requiring the knowledge of the containing atom - pass the symbol index into the linker's table from codegen via mir to emitter, to then utilise it in the linker.
2022-02-09stage2: implement all builtin floatops for f{16,32,64}John Schmidt
- Merge `floatop.zig` and `floatop_stage1.zig` since most tests now pass on stage2. - Add more behavior tests for a bunch of functions.
2022-02-07stage2: implement @sqrt for f{16,32,64}John Schmidt
Support for f128, comptime_float, and c_longdouble require improvements to compiler_rt and will implemented in a later PR. Some of the code in this commit could be made more generic, for instance `llvm.airSqrt` could probably be `llvm.airUnaryMath`, but let's cross that bridge when we get to it.
2022-02-07Merge pull request #10803 from ziglang/decl-has-lib-nameAndrew Kelley
stage2: store externs lib name as part of decl
2022-02-06stage2: add new Decl subtype, ExternFnJakub Konka
`ExternFn` will contain a maybe-lib-name if it was defined with the `extern` keyword like so ```zig extern "c" fn write(usize, usize, usize) usize; ``` `lib_name` will live as long as `ExternFn` decl does.
2022-02-06stage2 regalloc: Introduce error.OutOfRegistersjoachimschmidt557
2022-02-03stage2: remove the concept of register exceptionsJakub Konka
2022-01-30stage2 AArch64: Move to new regalloc freeze APIjoachimschmidt557
2022-01-30stage2: implement shl_exact and shr_exactAndrew Kelley
These produce an undefined value when one bits are shifted out. New AIR instruction: shr_exact.
2022-01-24stage2: rework a lot of stuffAndrew Kelley
AstGen: * rename the known_has_bits flag to known_non_opv to make it better reflect what it actually means. * add a known_comptime_only flag. * make the flags take advantage of identifiers of primitives and the fact that zig has no shadowing. * correct the known_non_opv flag for function bodies. Sema: * Rename `hasCodeGenBits` to `hasRuntimeBits` to better reflect what it does. - This function got a bit more complicated in this commit because of the duality of function bodies: on one hand they have runtime bits, but on the other hand they require being comptime known. * WipAnonDecl now takes a LazySrcDecl parameter and performs the type resolutions that it needs during finish(). * Implement comptime `@ptrToInt`. Codegen: * Improved handling of lowering decl_ref; make it work for comptime-known ptr-to-int values. - This same change had to be made many different times; perhaps we should look into merging the implementations of `genTypedValue` across x86, arm, aarch64, and riscv.
2022-01-18stage2: implement `@prefetch`Andrew Kelley
This reverts commit f423b5949b8722d4b290f57c3d06d015e39217b0, re-instating commit d48e4245b68bf25c7f41804a5012ac157a5ee546.
2022-01-18Revert "stage2: implement `@prefetch`"Andrew Kelley
This reverts commit d48e4245b68bf25c7f41804a5012ac157a5ee546. I have no idea why this is failing Drone CI, but in a branch, reverting this commit solved the problem.
2022-01-15stage2: implement `@prefetch`Andrew Kelley
2022-01-13stage2: fix build on 32-bit ISAsAndrew Kelley
Fixes regression introduced in 93b854eb745ab3294054ae71150fe60f134f4d10.
2022-01-12stage2: implement `@ctz` and `@clz` including SIMDAndrew Kelley
AIR: * `array_elem_val` is now allowed to be used with a vector as the array type. * New instructions: splat, vector_init AstGen: * The splat ZIR instruction uses coerced_ty for the ResultLoc, avoiding an unnecessary `as` instruction, since the coercion will be performed in Sema. * Builtins that accept vectors now ignore the type parameter. Comment from this commit reproduced here: The accepted proposal #6835 tells us to remove the type parameter from these builtins. To stay source-compatible with stage1, we still observe the parameter here, but we do not encode it into the ZIR. To implement this proposal in stage2, only AstGen code will need to be changed. Sema: * `clz` and `ctz` ZIR instructions are now handled by the same function which accept AIR tag and comptime eval function pointer to differentiate. * `@typeInfo` for vectors is implemented. * `@splat` is implemented. It takes advantage of `Value.Tag.repeated` 😎 * `elemValue` is implemented for vectors, when the index is a scalar. Handling a vector index is still TODO. * Element-wise coercion is implemented for vectors. It could probably be optimized a bit, but it is at least complete & correct. * `Type.intInfo` supports vectors, returning int info for the element. * `Value.ctz` initial implementation. Needs work. * `Value.eql` is implemented for arrays and vectors. LLVM backend: * Implement vector support when lowering `array_elem_val`. * Implement vector support when lowering `ctz` and `clz`. * Implement `splat` and `vector_init`.
2022-01-09stage2 codegen: fix airBlock bug in 3 backendsjoachimschmidt557
2022-01-08stage2: @errorName sema+llvmRobin Voetter
2021-12-27stage2: LLVM backend: implement `@tagName` for enumsAndrew Kelley
Introduced a new AIR instruction: `tag_name`. Reasons to do this instead of lowering it in Sema to a switch, function call, array lookup, or if-else tower: * Sema is a bottleneck; do less work in Sema whenever possible. * If any optimization passes run, and the operand to becomes comptime-known, then it could change to have a comptime result value instead of lowering to a function or array or something which would then have to be garbage-collected. * Backends may want to choose to use a function and a switch branch, or they may want to use a different strategy. Codegen for `@tagName` is implemented for the LLVM backend but not any others yet. Introduced some new `Type` tags: * `const_slice_u8_sentinel_0` * `manyptr_const_u8_sentinel_0` The motivation for this was to make typeof() on the tag_name AIR instruction non-allocating. A bunch more enum tests are passing now.
2021-12-21stage2: @shlWithOverflowRobin Voetter
2021-12-21stage2: @subWithOverflowRobin Voetter
2021-12-21stage2: @mulWithOverflowRobin Voetter
2021-12-21stage2: @returnAddress()Robin Voetter
2021-12-21stage2: @addWithOverflowRobin Voetter
2021-12-19stage2 AArch64: Implement saving callee-saved registersjoachimschmidt557
2021-11-30allocgate: std Allocator interface refactorLee Cannon
2021-11-30std lib API deprecations for the upcoming 0.9.0 releaseAndrew Kelley
See #3811
2021-11-12stage2 AArch64: add new load/store from/to stack MIR instructionsjoachimschmidt557
2021-11-10stage2 AArch64: implement airCondBrjoachimschmidt557
2021-11-10stage2 AArch64: implement genSetReg for condition flagsjoachimschmidt557
2021-11-10stage2 AArch64: implement airCmpjoachimschmidt557
2021-11-10macho: use start.zig for macOS entrypointJakub Konka
This effectively allows us to compile ```zig pub fn main() void {} ``` which then calls into `std.start`. Changes required to make this happen: * handle signed int to immediate in x86_64 and aarch64 codegen * ensure that on arm64 macOS, `.x19` is a caller-preserved register - I'm not sure about that one at all and would like to brainstorm it with anyone interested and especially Joachim. * finally, fix a bug in the linker - mark new got entry as dirty upon atom growth.
2021-11-09Sema: implement coerce_result_ptr for optionalsAndrew Kelley
New AIR instruction: `optional_payload_ptr_set` It's like `optional_payload_ptr` except it sets the non-null bit. When storing to the payload via a result location that is an optional, `optional_payload_ptr_set` is now emitted. There is a new algorithm in `zirCoerceResultPtr` which stores a dummy value through the result pointer into a temporary block, and then pops off the AIR instructions from the temporary block in order to determine how to transform the result location pointer in case any in-between coercions need to happen. Fixes a couple of behavior tests regarding optionals.
2021-11-01stage2 AArch64: implement unconditional branchesjoachimschmidt557
2021-10-31stage2 AArch64: introduce Emit.fail for handling errors in MIR emitjoachimschmidt557