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| author | Andrew Kelley <andrew@ziglang.org> | 2022-01-30 16:23:31 -0700 |
|---|---|---|
| committer | Andrew Kelley <andrew@ziglang.org> | 2022-01-30 16:23:31 -0700 |
| commit | fb7060d3c2e8ce4d7de5560adf8ec4a26fc5f6e8 (patch) | |
| tree | 3710af0870e1e1d43f44830d6ff3e662761e93ce /src/arch/aarch64/CodeGen.zig | |
| parent | 0c30799d4039c30f95eee29e2c2f8f604e8b9880 (diff) | |
| download | zig-fb7060d3c2e8ce4d7de5560adf8ec4a26fc5f6e8.tar.gz zig-fb7060d3c2e8ce4d7de5560adf8ec4a26fc5f6e8.zip | |
stage2: implement shl_exact and shr_exact
These produce an undefined value when one bits are shifted out.
New AIR instruction: shr_exact.
Diffstat (limited to 'src/arch/aarch64/CodeGen.zig')
| -rw-r--r-- | src/arch/aarch64/CodeGen.zig | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/arch/aarch64/CodeGen.zig b/src/arch/aarch64/CodeGen.zig index cb686b8242..145fb2e931 100644 --- a/src/arch/aarch64/CodeGen.zig +++ b/src/arch/aarch64/CodeGen.zig @@ -535,12 +535,12 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void { .cmp_gt => try self.airCmp(inst, .gt), .cmp_neq => try self.airCmp(inst, .neq), - .bool_and => try self.airBoolOp(inst), - .bool_or => try self.airBoolOp(inst), - .bit_and => try self.airBitAnd(inst), - .bit_or => try self.airBitOr(inst), - .xor => try self.airXor(inst), - .shr => try self.airShr(inst), + .bool_and => try self.airBoolOp(inst), + .bool_or => try self.airBoolOp(inst), + .bit_and => try self.airBitAnd(inst), + .bit_or => try self.airBitOr(inst), + .xor => try self.airXor(inst), + .shr, .shr_exact => try self.airShr(inst), .alloc => try self.airAlloc(inst), .ret_ptr => try self.airRetPtr(inst), |