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| author | joachimschmidt557 <joachim.schmidt557@outlook.com> | 2021-11-07 17:57:21 +0100 |
|---|---|---|
| committer | joachimschmidt557 <joachim.schmidt557@outlook.com> | 2021-11-10 19:48:16 +0100 |
| commit | a5a012e8599e57da3e80ff770f9de492037e4f4a (patch) | |
| tree | 86fb5332cb15054858b25900829344678d901e69 /src/arch/aarch64/CodeGen.zig | |
| parent | 8cb00519cddadae8728d2b2e51a36da71d5bfe67 (diff) | |
| download | zig-a5a012e8599e57da3e80ff770f9de492037e4f4a.tar.gz zig-a5a012e8599e57da3e80ff770f9de492037e4f4a.zip | |
stage2 AArch64: implement genSetReg for condition flags
Diffstat (limited to 'src/arch/aarch64/CodeGen.zig')
| -rw-r--r-- | src/arch/aarch64/CodeGen.zig | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/arch/aarch64/CodeGen.zig b/src/arch/aarch64/CodeGen.zig index 4d56e592ef..dba0c86552 100644 --- a/src/arch/aarch64/CodeGen.zig +++ b/src/arch/aarch64/CodeGen.zig @@ -2182,6 +2182,25 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void else => unreachable, // unexpected register size } }, + .compare_flags_unsigned, + .compare_flags_signed, + => |op| { + const condition = switch (mcv) { + .compare_flags_unsigned => Instruction.Condition.fromCompareOperatorUnsigned(op), + .compare_flags_signed => Instruction.Condition.fromCompareOperatorSigned(op), + else => unreachable, + }; + + _ = try self.addInst(.{ + .tag = .cset, + .data = .{ .rrr_cond = .{ + .rd = reg, + .rn = .xzr, + .rm = .xzr, + .cond = condition, + } }, + }); + }, .immediate => |x| { _ = try self.addInst(.{ .tag = .movz, |