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-rw-r--r--src/codegen.zig2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/codegen.zig b/src/codegen.zig
index d5b106dbe3..11c007dbed 100644
--- a/src/codegen.zig
+++ b/src/codegen.zig
@@ -1247,6 +1247,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
const bin_op = self.air.instructions.items(.data)[inst].bin_op;
const result: MCValue = if (self.liveness.isUnused(inst)) .dead else switch (arch) {
.arm, .armeb => try self.genArmBinOp(inst, bin_op.lhs, bin_op.rhs, .bit_and),
+ .x86_64 => try self.genX8664BinMath(inst, bin_op.lhs, bin_op.rhs),
else => return self.fail("TODO implement bitwise and for {}", .{self.target.cpu.arch}),
};
return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
@@ -1256,6 +1257,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
const bin_op = self.air.instructions.items(.data)[inst].bin_op;
const result: MCValue = if (self.liveness.isUnused(inst)) .dead else switch (arch) {
.arm, .armeb => try self.genArmBinOp(inst, bin_op.lhs, bin_op.rhs, .bit_or),
+ .x86_64 => try self.genX8664BinMath(inst, bin_op.lhs, bin_op.rhs),
else => return self.fail("TODO implement bitwise or for {}", .{self.target.cpu.arch}),
};
return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });