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| author | Jacob G-W <jacoblevgw@gmail.com> | 2021-08-18 21:29:32 -0400 |
|---|---|---|
| committer | Veikka Tuominen <git@vexu.eu> | 2021-08-19 22:21:16 +0300 |
| commit | df10e998ee4a935f49943fb5c0ef134f336c6ee3 (patch) | |
| tree | 906dfb30f30a6da36308eee7f1ea22ace0f80a0d /src/codegen.zig | |
| parent | 62fe4a0ba8a08b9477e772841d3ae128937f0752 (diff) | |
| download | zig-df10e998ee4a935f49943fb5c0ef134f336c6ee3.tar.gz zig-df10e998ee4a935f49943fb5c0ef134f336c6ee3.zip | |
stage2 x86_64: enable bitwise and + or and add tests
Diffstat (limited to 'src/codegen.zig')
| -rw-r--r-- | src/codegen.zig | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/codegen.zig b/src/codegen.zig index d5b106dbe3..11c007dbed 100644 --- a/src/codegen.zig +++ b/src/codegen.zig @@ -1247,6 +1247,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { const bin_op = self.air.instructions.items(.data)[inst].bin_op; const result: MCValue = if (self.liveness.isUnused(inst)) .dead else switch (arch) { .arm, .armeb => try self.genArmBinOp(inst, bin_op.lhs, bin_op.rhs, .bit_and), + .x86_64 => try self.genX8664BinMath(inst, bin_op.lhs, bin_op.rhs), else => return self.fail("TODO implement bitwise and for {}", .{self.target.cpu.arch}), }; return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none }); @@ -1256,6 +1257,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { const bin_op = self.air.instructions.items(.data)[inst].bin_op; const result: MCValue = if (self.liveness.isUnused(inst)) .dead else switch (arch) { .arm, .armeb => try self.genArmBinOp(inst, bin_op.lhs, bin_op.rhs, .bit_or), + .x86_64 => try self.genX8664BinMath(inst, bin_op.lhs, bin_op.rhs), else => return self.fail("TODO implement bitwise or for {}", .{self.target.cpu.arch}), }; return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none }); |