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-rw-r--r--src/arch/aarch64/CodeGen.zig19
1 files changed, 19 insertions, 0 deletions
diff --git a/src/arch/aarch64/CodeGen.zig b/src/arch/aarch64/CodeGen.zig
index 4d56e592ef..dba0c86552 100644
--- a/src/arch/aarch64/CodeGen.zig
+++ b/src/arch/aarch64/CodeGen.zig
@@ -2182,6 +2182,25 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
else => unreachable, // unexpected register size
}
},
+ .compare_flags_unsigned,
+ .compare_flags_signed,
+ => |op| {
+ const condition = switch (mcv) {
+ .compare_flags_unsigned => Instruction.Condition.fromCompareOperatorUnsigned(op),
+ .compare_flags_signed => Instruction.Condition.fromCompareOperatorSigned(op),
+ else => unreachable,
+ };
+
+ _ = try self.addInst(.{
+ .tag = .cset,
+ .data = .{ .rrr_cond = .{
+ .rd = reg,
+ .rn = .xzr,
+ .rm = .xzr,
+ .cond = condition,
+ } },
+ });
+ },
.immediate => |x| {
_ = try self.addInst(.{
.tag = .movz,