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| author | Andrew Kelley <andrew@ziglang.org> | 2021-09-29 15:33:45 -0700 |
|---|---|---|
| committer | Andrew Kelley <andrew@ziglang.org> | 2021-09-29 15:33:45 -0700 |
| commit | bdbedff910e18e18dc31db84a80607435e9b6ee0 (patch) | |
| tree | d0081d6089f09f797662b6f22d05a73895e5aacd /src/type.zig | |
| parent | ea6706b6f406606a7523e35e34e390fb880b607e (diff) | |
| download | zig-bdbedff910e18e18dc31db84a80607435e9b6ee0.tar.gz zig-bdbedff910e18e18dc31db84a80607435e9b6ee0.zip | |
stage2: LLVM backend: properly set module target data
Also fix tripping LLVM assert having to do with 0 bit integers.
stage2 behavior tests now run clean in a debug build of llvm 12.
Diffstat (limited to 'src/type.zig')
| -rw-r--r-- | src/type.zig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/type.zig b/src/type.zig index cd7eb7a7d0..dacde84167 100644 --- a/src/type.zig +++ b/src/type.zig @@ -3868,6 +3868,7 @@ pub const Type = extern union { }; pub const @"bool" = initTag(.bool); + pub const @"usize" = initTag(.usize); pub const @"comptime_int" = initTag(.comptime_int); pub fn ptr(arena: *Allocator, d: Payload.Pointer.Data) !Type { |