Merge pull request #10639 from Vexu/f80

Add f80

1 files changed, 11 insertions, 0 deletions

diff --git a/src/stage1/target.cpp b/src/stage1/target.cpp
index feb2c7f143..a505b4bd21 100644
--- a/src/stage1/target.cpp
+++ b/src/stage1/target.cpp
@@ -1019,6 +1019,17 @@ bool target_long_double_is_f128(const ZigTarget *target) {
     }
 }
 
+bool target_has_f80(const ZigTarget *target) {
+    switch (target->arch) {
+        case ZigLLVM_x86:
+        case ZigLLVM_x86_64:
+            return true;
+
+        default:
+            return false;
+    }
+}
+
 bool target_is_riscv(const ZigTarget *target) {
     return target->arch == ZigLLVM_riscv32 || target->arch == ZigLLVM_riscv64;
 }