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authorJakub Konka <kubkon@jakubkonka.com>2020-11-06 23:03:20 +0100
committerJakub Konka <kubkon@jakubkonka.com>2020-11-11 14:34:53 +0100
commitd601b0f4eb025c753ca9f139480578511122afad (patch)
tree1890aa22a1f01f8c6a42de119b43b71320ccdaed /src/codegen.zig
parent68bb1e91aaafbf57dc26cde7233e2deaf951b3a6 (diff)
downloadzig-d601b0f4eb025c753ca9f139480578511122afad.tar.gz
zig-d601b0f4eb025c753ca9f139480578511122afad.zip
Add basic genSetReg for aarch64
Diffstat (limited to 'src/codegen.zig')
-rw-r--r--src/codegen.zig19
1 files changed, 19 insertions, 0 deletions
diff --git a/src/codegen.zig b/src/codegen.zig
index 6a7b67aee2..47d33570d5 100644
--- a/src/codegen.zig
+++ b/src/codegen.zig
@@ -2489,6 +2489,25 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
},
else => return self.fail(src, "TODO implement getSetReg for arm {}", .{mcv}),
},
+ .aarch64 => switch (mcv) {
+ .dead => unreachable,
+ .ptr_stack_offset => unreachable,
+ .ptr_embedded_in_code => unreachable,
+ .unreach, .none => return, // Nothing to do.
+ .undef => {
+ if (!self.wantSafety())
+ return; // The already existing value will do just fine.
+ // Write the debug undefined value.
+ switch (reg.size()) {
+ 32 => return self.genSetReg(src, reg, .{ .immediate = 0xaaaaaaaa }),
+ 64 => return self.genSetReg(src, reg, .{ .immediate = 0xaaaaaaaaaaaaaaaa }),
+ else => unreachable, // unexpected register size
+ }
+ },
+ .immediate => return self.fail(src, "TODO implement genSetReg for aarch64 {}", .{mcv}),
+ .register => return self.fail(src, "TODO implement genSetReg for aarch64 {}", .{mcv}),
+ else => return self.fail(src, "TODO implement genSetReg for aarch64 {}", .{mcv}),
+ },
.riscv64 => switch (mcv) {
.dead => unreachable,
.ptr_stack_offset => unreachable,