From d601b0f4eb025c753ca9f139480578511122afad Mon Sep 17 00:00:00 2001 From: Jakub Konka Date: Fri, 6 Nov 2020 23:03:20 +0100 Subject: Add basic genSetReg for aarch64 --- src/codegen.zig | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'src/codegen.zig') diff --git a/src/codegen.zig b/src/codegen.zig index 6a7b67aee2..47d33570d5 100644 --- a/src/codegen.zig +++ b/src/codegen.zig @@ -2489,6 +2489,25 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { }, else => return self.fail(src, "TODO implement getSetReg for arm {}", .{mcv}), }, + .aarch64 => switch (mcv) { + .dead => unreachable, + .ptr_stack_offset => unreachable, + .ptr_embedded_in_code => unreachable, + .unreach, .none => return, // Nothing to do. + .undef => { + if (!self.wantSafety()) + return; // The already existing value will do just fine. + // Write the debug undefined value. + switch (reg.size()) { + 32 => return self.genSetReg(src, reg, .{ .immediate = 0xaaaaaaaa }), + 64 => return self.genSetReg(src, reg, .{ .immediate = 0xaaaaaaaaaaaaaaaa }), + else => unreachable, // unexpected register size + } + }, + .immediate => return self.fail(src, "TODO implement genSetReg for aarch64 {}", .{mcv}), + .register => return self.fail(src, "TODO implement genSetReg for aarch64 {}", .{mcv}), + else => return self.fail(src, "TODO implement genSetReg for aarch64 {}", .{mcv}), + }, .riscv64 => switch (mcv) { .dead => unreachable, .ptr_stack_offset => unreachable, -- cgit v1.2.3