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| author | Andrew Kelley <andrew@ziglang.org> | 2019-09-29 12:21:22 -0400 |
|---|---|---|
| committer | Andrew Kelley <andrew@ziglang.org> | 2019-09-29 12:21:22 -0400 |
| commit | bd46c1c328d8e7a0c3393193fd2f963c1077b030 (patch) | |
| tree | ab51b11862dc04ddb627d4e412873b903f63c2b5 /src/analyze.cpp | |
| parent | 543e729398c2ae2a6fbae8ab54ce0737d35004a0 (diff) | |
| download | zig-bd46c1c328d8e7a0c3393193fd2f963c1077b030.tar.gz zig-bd46c1c328d8e7a0c3393193fd2f963c1077b030.zip | |
RISC-V: get to the linking phase of behavior tests
See #3338 and #3339
Diffstat (limited to 'src/analyze.cpp')
| -rw-r--r-- | src/analyze.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/analyze.cpp b/src/analyze.cpp index 82872bcbfc..1282126fbc 100644 --- a/src/analyze.cpp +++ b/src/analyze.cpp @@ -916,7 +916,7 @@ bool want_first_arg_sret(CodeGen *g, FnTypeId *fn_type_id) { if (g->zig_target->arch == ZigLLVM_x86_64) { X64CABIClass abi_class = type_c_abi_x86_64_class(g, fn_type_id->return_type); return abi_class == X64CABIClass_MEMORY; - } else if (target_is_arm(g->zig_target)) { + } else if (target_is_arm(g->zig_target) || target_is_riscv(g->zig_target)) { return type_size(g, fn_type_id->return_type) > 16; } else if (g->zig_target->arch == ZigLLVM_mipsel) { return false; |