From bd46c1c328d8e7a0c3393193fd2f963c1077b030 Mon Sep 17 00:00:00 2001 From: Andrew Kelley Date: Sun, 29 Sep 2019 12:21:22 -0400 Subject: RISC-V: get to the linking phase of behavior tests See #3338 and #3339 --- src/analyze.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/analyze.cpp') diff --git a/src/analyze.cpp b/src/analyze.cpp index 82872bcbfc..1282126fbc 100644 --- a/src/analyze.cpp +++ b/src/analyze.cpp @@ -916,7 +916,7 @@ bool want_first_arg_sret(CodeGen *g, FnTypeId *fn_type_id) { if (g->zig_target->arch == ZigLLVM_x86_64) { X64CABIClass abi_class = type_c_abi_x86_64_class(g, fn_type_id->return_type); return abi_class == X64CABIClass_MEMORY; - } else if (target_is_arm(g->zig_target)) { + } else if (target_is_arm(g->zig_target) || target_is_riscv(g->zig_target)) { return type_size(g, fn_type_id->return_type) > 16; } else if (g->zig_target->arch == ZigLLVM_mipsel) { return false; -- cgit v1.2.3