diff options
| author | Andrew Kelley <andrew@ziglang.org> | 2019-11-25 18:46:17 -0500 |
|---|---|---|
| committer | Andrew Kelley <andrew@ziglang.org> | 2019-11-25 18:46:17 -0500 |
| commit | 4261fa3c49be715355c9623102bad0bf93d537a3 (patch) | |
| tree | ba8da3ef0611a547fe67c61ed2d42d4ea67e6d2e /src/analyze.cpp | |
| parent | 659c1bdeeebce7bf32e122be6a728fe727112c56 (diff) | |
| download | zig-4261fa3c49be715355c9623102bad0bf93d537a3.tar.gz zig-4261fa3c49be715355c9623102bad0bf93d537a3.zip | |
move logic to the appropriate layers; add new compile error
Diffstat (limited to 'src/analyze.cpp')
| -rw-r--r-- | src/analyze.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/analyze.cpp b/src/analyze.cpp index e47b67a495..e1b086059b 100644 --- a/src/analyze.cpp +++ b/src/analyze.cpp @@ -978,7 +978,8 @@ bool want_first_arg_sret(CodeGen *g, FnTypeId *fn_type_id) { if (g->zig_target->arch == ZigLLVM_x86 || g->zig_target->arch == ZigLLVM_x86_64 || target_is_arm(g->zig_target) || - target_is_riscv(g->zig_target)) + target_is_riscv(g->zig_target) || + target_is_wasm(g->zig_target)) { X64CABIClass abi_class = type_c_abi_x86_64_class(g, fn_type_id->return_type); return abi_class == X64CABIClass_MEMORY || abi_class == X64CABIClass_MEMORY_nobyval; |