From 4261fa3c49be715355c9623102bad0bf93d537a3 Mon Sep 17 00:00:00 2001 From: Andrew Kelley Date: Mon, 25 Nov 2019 18:46:17 -0500 Subject: move logic to the appropriate layers; add new compile error --- src/analyze.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/analyze.cpp') diff --git a/src/analyze.cpp b/src/analyze.cpp index e47b67a495..e1b086059b 100644 --- a/src/analyze.cpp +++ b/src/analyze.cpp @@ -978,7 +978,8 @@ bool want_first_arg_sret(CodeGen *g, FnTypeId *fn_type_id) { if (g->zig_target->arch == ZigLLVM_x86 || g->zig_target->arch == ZigLLVM_x86_64 || target_is_arm(g->zig_target) || - target_is_riscv(g->zig_target)) + target_is_riscv(g->zig_target) || + target_is_wasm(g->zig_target)) { X64CABIClass abi_class = type_c_abi_x86_64_class(g, fn_type_id->return_type); return abi_class == X64CABIClass_MEMORY || abi_class == X64CABIClass_MEMORY_nobyval; -- cgit v1.2.3