aboutsummaryrefslogtreecommitdiff
path: root/test/behavior/bugs/12776.zig
blob: 2061d6e8041803031e86bfe886a1d2402f8212a2 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
const std = @import("std");
const builtin = @import("builtin");

const RAM = struct {
    data: [0xFFFF + 1]u8,
    fn new() !RAM {
        return RAM{ .data = [_]u8{0} ** 0x10000 };
    }
    fn get(self: *RAM, addr: u16) u8 {
        return self.data[addr];
    }
};

const CPU = packed struct {
    interrupts: bool,
    ram: *RAM,
    fn new(ram: *RAM) !CPU {
        return CPU{
            .ram = ram,
            .interrupts = false,
        };
    }
    fn tick(self: *CPU) !void {
        var queued_interrupts = self.ram.get(0xFFFF) & self.ram.get(0xFF0F);
        if (self.interrupts and queued_interrupts != 0) {
            self.interrupts = false;
        }
    }
};

test {
    if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
    if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
    if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest;
    if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
    if (builtin.zig_backend == .stage2_x86_64) {
        // Careful enabling this test, fails randomly.
        return error.SkipZigTest;
    }

    var ram = try RAM.new();
    var cpu = try CPU.new(&ram);
    try cpu.tick();
    try std.testing.expect(cpu.interrupts == false);
}