| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2022-04-28 | test: migrate arm incremental tests | Jakub Konka | |
| 2022-01-24 | stage2: rework a lot of stuff | Andrew Kelley | |
| AstGen: * rename the known_has_bits flag to known_non_opv to make it better reflect what it actually means. * add a known_comptime_only flag. * make the flags take advantage of identifiers of primitives and the fact that zig has no shadowing. * correct the known_non_opv flag for function bodies. Sema: * Rename `hasCodeGenBits` to `hasRuntimeBits` to better reflect what it does. - This function got a bit more complicated in this commit because of the duality of function bodies: on one hand they have runtime bits, but on the other hand they require being comptime known. * WipAnonDecl now takes a LazySrcDecl parameter and performs the type resolutions that it needs during finish(). * Implement comptime `@ptrToInt`. Codegen: * Improved handling of lowering decl_ref; make it work for comptime-known ptr-to-int values. - This same change had to be made many different times; perhaps we should look into merging the implementations of `genTypedValue` across x86, arm, aarch64, and riscv. | |||
| 2022-01-02 | stage2 ARM: implement wrap_errunion_err for empty payloads | joachimschmidt557 | |
| 2022-01-01 | stage2 ARM: implement airUnwrapErrErr + airCmp for error sets | joachimschmidt557 | |
| 2022-01-01 | stage2 ARM: implement airCall for function pointers | joachimschmidt557 | |
| 2021-12-30 | stage2 ARM: implement struct_field_ptr and struct_field_val | joachimschmidt557 | |
| 2021-12-28 | stage2 ARM: implement slice_elem_val for types with size <= 4 | joachimschmidt557 | |
| 2021-12-21 | stage2 ARM: implement is_err and is_non_err for simple error unions | joachimschmidt557 | |
| 2021-12-21 | stage2 ARM: implement is_null and is_non_null for ptr-like optionals | joachimschmidt557 | |
| 2021-12-18 | stage2 ARM: spill insts currently in compare flags if necessary | joachimschmidt557 | |
| 2021-12-04 | stage2 ARM: Implement calling with stack parameters | joachimschmidt557 | |
| 2021-08-20 | stage2 codegen: re-allocate result register in finishAir | joachimschmidt557 | |
| In some cases (such as bitcast), an operand may be the same MCValue as the result. If that operand died and was a register, it was freed by processDeath. We have to "re-allocate" the register. | |||
| 2021-08-20 | stage2 ARM: add test cases for bit shifts | joachimschmidt557 | |
| 2021-07-30 | stage2 codegen: Implement genTypedValue for enums | joachimschmidt557 | |
| 2021-05-17 | Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgen | Andrew Kelley | |
| Conflicts: * src/codegen/spirv.zig * src/link/SpirV.zig We're going to want to improve the stage2 test harness to print the source file name when a compile error occurs otherwise std lib contributors are going to see some confusing CI failures when they cause stage2 AstGen compile errors. | |||
| 2021-05-17 | stage2: test cases take advantage of `pub fn main` support | Andrew Kelley | |
| 2021-05-17 | stage2 ARM: correct spilling in genArmMul as well | joachimschmidt557 | |
| 2021-05-12 | stage2: fix test cases to add `pub` on exported _start fn | Andrew Kelley | |
| This way the start code respects them. | |||
| 2021-05-09 | stage2 ARM: Add spill registers test | joachimschmidt557 | |
| 2021-04-11 | stage2 ARM: Add fibonacci test | joachimschmidt557 | |
| 2021-03-31 | stage2 codegen: Make sure function return value is in a callee | joachimschmidt557 | |
| preserved register | |||
| 2021-03-02 | stage2 ARM: Add tests for basic integer multiplication | joachimschmidt557 | |
| 2021-01-19 | astgen: eliminate rlWrapPtr and all its callsites | Andrew Kelley | |
| The following AST avoids unnecessary derefs now: * error set decl * field access * array access * for loops: replace ensure_indexable and deref on the len_ptr with a special purpose ZIR instruction called indexable_ptr_len. Added an error note when for loop operand is the wrong type. I also accidentally implemented `@field`. | |||
| 2021-01-01 | stage2 ARM: Add simple tests for conditional branching | joachimschmidt557 | |
| 2020-12-21 | stage2 ARM: add test cases for binary bitwise operations | joachimschmidt557 | |
| 2020-11-28 | stage2 ARM: add test case for addition | joachimschmidt557 | |
| 2020-10-03 | stage2 ARM: add testcases for non-leaf fns, parameters, return values | joachimschmidt557 | |
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index : zig | |
| General-purpose programming language and toolchain for maintaining robust, optimal, and reusable software. https://ziglang.org |
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