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Age	Commit message (Collapse)	Author
2024-06-13	riscv: `std.fmt.format` running	David Rubin
	- implements `airSlice`, `airBitAnd`, `airBitOr`, `airShr`. - got a basic design going for the `airErrorName` but for some reason it simply returns empty bytes. will investigate further. - only generating `.got.zig` entries when not compiling an object or shared library - reduced the total amount of ops a mnemonic can have to 3, simplifying the logic
2024-05-11	riscv: add stage2_riscv to test matrix and bypass failing tests	David Rubin

2023-10-15	spirv: update failing / passing tests	Robin Voetter
	Some tests are now failing due to debug info changes, some tests now pass due to improved compiler functionality.
2023-05-11	setup spirv backend in behavior tests	Ali Chraghi

2023-03-21	x86_64: implement atomic and fence ops	Jacob Young

2022-12-27	stage2 AArch64: unify callee-preserved regs on all targets	joachimschmidt557
	also enables many passing behavior tests
2022-12-10	stage2: sparc64: Skip unimplemented tests	Koakuma

2022-09-09	stage2 ARM: amend implementation of various AIR instructions	joachimschmidt557
	- unwrap_errunion_err for registers - unwrap_errunion_payload for registers - ptr_slice_len_ptr for all MCValues - ptr_slice_ptr_ptr for all MCValues
2022-03-17	CBE: enable more tests that are currently passing	Daniele Cocca

2022-03-09	wasm: Enable passing behavior tests	Luuk de Gram
	This also adds some float-related instructions to MIR/Emit
2021-04-29	move behavior tests from test/stage1/ to test/	Andrew Kelley
	And fix test cases to make them pass. This is in preparation for starting to pass behavior tests with self-hosted.