aboutsummaryrefslogtreecommitdiff
path: root/test/behavior/basic.zig
AgeCommit message (Collapse)Author
2022-09-09stage2 ARM: implement ptr_elem_valjoachimschmidt557
2022-09-09stage2 ARM: implement struct_field_val for registersjoachimschmidt557
2022-09-09stage2 ARM: amend implementation of various AIR instructionsjoachimschmidt557
- unwrap_errunion_err for registers - unwrap_errunion_payload for registers - ptr_slice_len_ptr for all MCValues - ptr_slice_ptr_ptr for all MCValues
2022-08-16Sema: ignore current declaration in ambiguous reference errorVeikka Tuominen
Closes #12429
2022-07-23disable flaky behavior testAndrew Kelley
see #12208
2022-07-05disable regressed wasm32 behavior tests from LLVM 14Andrew Kelley
2022-06-28Revert "AstGen: preserve inferred ptr result loc for breaks"Andrew Kelley
This reverts commit 8bf3e1f8d0902abd4133e2729b3625c25011c3ff, which introduced miscompilations for peer expressions any time they needed coercions to runtime types. I opened #11957 as a proposal to accomplish the goal of the reverted commit. Closes #11898
2022-06-25stage2 ARM: implement basic intCast and error union wrappingjoachimschmidt557
2022-06-24stage2: sparc64: Skip Sema-failing tests for nowKoakuma
2022-06-11Sema: skip decl causing namespace lookup when doing lookupVeikka Tuominen
2022-06-06Sema: fix inline call of func using ret_ptr with comptime only typeVeikka Tuominen
2022-06-06AstGen: fix coercion scope type when stores are eliminatedVeikka Tuominen
2022-06-06Sema: fix coerce result ptr outside of functionsVeikka Tuominen
2022-06-01Sema: apply previous changes to `validateUnionInit`Veikka Tuominen
2022-05-31stage2: ignore generic return type when hashing function typeVeikka Tuominen
Generic parameter types are already ignored.
2022-05-31Sema: take `dbg_stmt` into account in `zirResolveInferredAlloc`Veikka Tuominen
2022-05-29AstGen: add tuple aware elem_type_indexVeikka Tuominen
2022-05-29AstGen: improve generated Zir for array init exprsVeikka Tuominen
2022-05-27stage2 AArch64: complete genTypedValuejoachimschmidt557
2022-05-27AstGen: preserve inferred ptr result loc for breaksVeikka Tuominen
2022-05-19x64: re-enable behavior testsJakub Konka
2022-05-17LLVM: support mixing extern and export with the same symbol nameAndrew Kelley
2022-04-29Sema: Fix many-pointer array concatenation at comptime (#11512)sin-ack
* Sema: Correctly determine whether array_cat lhs and rhs are single ptrs Many-pointers are also not single-pointers and wouldn't be considered here. This commit makes the conditions use the appropriately-named isSinglePointer instead. * Sema: Correctly obtain ArrayInfo for many-pointer concatenation Many-pointers at comptime have a known size like slices and can be used in array concatenation. This fixes a stage1 regression. * test: Add comptime manyptr concatenation test Co-authored-by: sin-ack <sin-ack@users.noreply.github.com>
2022-04-19stage2 AArch64: Add ldrsb, ldrsh instructionsjoachimschmidt557
2022-04-19stage2 AArch64: Implement basic truncate functionalityjoachimschmidt557
2022-04-15AstGen: handle rl_ty_inst for mutable variablesVeikka Tuominen
2022-03-28AstGen: coerce break operands of labeled blocksAndrew Kelley
Similar code was already in place for conditional branches. This updates AstGen to do the same for labeled blocks. It takes advantage of the `store_to_block_ptr` instructions by mutating them in place to become `as` instructions, coercing the break operands before they are returned from the block.
2022-03-28AstGen: clear rl_ty_inst in setBreakResultLoc if one is not providedVeikka Tuominen
2022-03-26wasm: Enable passing testsLuuk de Gram
2022-03-21stage2: x86_64: update passing tests after implementing ptr_elem_valmparadinha
the 3 tests that called `testArray2DConstDoublePtr` started passing after implementing `ptr_elem_val`. the rest of these I think were already passing before.
2022-03-19Sema: add error for runtime block peer type being comptime onlyVeikka Tuominen
2022-03-18stage2 ARM: implement slice_elem_ptr, ptr_elem_ptrjoachimschmidt557
2022-03-18stage2: improve `@typeName`Andrew Kelley
* make it always return a fully qualified name. stage1 is inconsistent about this. * AstGen: fix anon_name_strategy to correctly be `func` when anon type creation happens in the operand of the return expression. * Sema: implement type names for the "function" naming strategy. * Put "enum", "union", "opaque", or "struct" in place of "anon" when creating respective anonymous Decl names. * std.testing: add `expectStringStartsWith`. Didn't end up using it after all. Also this enables the real test runner for stage2 LLVM backend (sans wasm32) since it works now.
2022-03-17wasm: Implement 'memcpy' instructionLuuk de Gram
This implements the `memcpy` instruction and also updates the inline memcpy calls to make use of the same implementation. We use the fast-loop when the length is comptime known, and use a runtime loop when the length is runtime known. We also perform feature-dection to emit a simply wasm memory.copy instruction when the feature 'bulk-memory' is enabled. (off by default).
2022-03-11stage2: passing threadlocal tests for x86_64-linuxAndrew Kelley
* use the real start code for LLVM backend with x86_64-linux - there is still a check for zig_backend after initializing the TLS area to skip some stuff. * introduce new AIR instructions and implement them for the LLVM backend. They are the same as `call` except with a modifier. - call_always_tail - call_never_tail - call_never_inline * LLVM backend calls hasRuntimeBitsIgnoringComptime in more places to avoid unnecessarily depending on comptimeOnly being resolved for some types. * LLVM backend: remove duplicate code for setting linkage and value name. The canonical place for this is in `updateDeclExports`. * LLVM backend: do some assembly template massaging to make `%%` rendered as `%`. More hacks will be needed to make inline assembly catch up with stage1.
2022-03-10stage2: implement integer pointer constantsAndrew Kelley
2022-03-09Sema: implement pointer to tuple to pointer to array coercionAndrew Kelley
This involved an LLVM backend fix for the aggregate_init instruction.
2022-03-09AstGen: ensure lableld block implicitly ends in a breakVeikka Tuominen
2022-03-08stage2 ARM: implement ret_loadjoachimschmidt557
2022-03-03stage2: make analyzePtrArithmetic no-op with offset=0Veikka Tuominen
2022-03-02stage2 parser: UTF-8 encode \u{NNNNNN} escape sequencesCody Tapscott
The core of this change is to re-use the escape sequence parsing logic for parsing both string and character literals. The actual fix is that UTF-8 encoding was missing for string literals with \u{...} escape sequences.
2022-03-02x64: rectify and add missing optionals bitsJakub Konka
Includes changes/additions to: * `wrap_optional` * `optional_payload` * `isNull` helper
2022-03-01LLVM: add extra padding to structs and tuples sometimesAndrew Kelley
* Sema: resolve type fully when emitting an alloc AIR instruction to avoid tripping assertion for checking struct field alignment. * LLVM backend: keep a reference to the LLVM target data alive during lowering so that we can ask LLVM what it thinks the ABI alignment and size of LLVM types are. We need this in order to lower tuples and structs so that we can put in extra padding bytes when Zig disagrees with LLVM about the size or alignment of something. * LLVM backend: make the LLVM struct type packed that contains the most aligned union field and the padding. This prevents the struct from being too big according to LLVM. In the future, we may want to consider instead emitting unions in a "flat" manner; putting the tag, most aligned union field, and padding all in the same struct field space. * LLVM backend: make structs with 2 or fewer fields return isByRef=false. This results in more efficient codegen. This required lowering of bitcast to sometimes store the struct into an alloca, ptrcast, and then load because LLVM does not allow bitcasting structs. * enable more passing behavior tests.
2022-03-01x64: impl airMemset using inline memsetJakub Konka
2022-03-01stage2 ARM: implement return types with abi size > 4joachimschmidt557
2022-02-28x64: pass more behavior testsJakub Konka
2022-02-27stage2 ARM: enable more behavior testsjoachimschmidt557
2022-02-27stage2: forward discard result loc to more expressionsVeikka Tuominen
2022-02-26stage2 ARM: generate correct variants of ldr instructionjoachimschmidt557
When loading an i16 for example, generate ldrsh instead of ldrh
2022-02-26stage2 ARM: implement truncate to ints with bits <= 32joachimschmidt557