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path: root/src/zir_sema.zig
AgeCommit message (Expand)Author
2020-12-28Revert "stage2: add compile log statement (#7191)"Andrew Kelley
2020-12-28stage2: make Alloc(Inferred) have mutabality info (#7570)g-w1
2020-12-26make compileError use an UnOp since its operand is just a *Instg-w1
2020-12-26add test for @compileError in zig code, not only zirg-w1
2020-12-26change zir definition to use *Inst instead of []const u8g-w1
2020-12-26stage2: add compile log statement (#7191)g-w1
2020-12-23Merge pull request #7507 from joachimschmidt557/stage2-armVeikka Tuominen
2020-12-23stage2: @TypeOf (#7475)g-w1
2020-12-21stage2 ARM: implement basic binary bitwise operationsjoachimschmidt557
2020-11-17stage2: initial container astgenVexu
2020-10-30stage2: return same hash for different representations of same valueVexu
2020-10-30stage2: switch comptime executionVexu
2020-10-30stage2: implement switch validation for integersVexu
2020-10-30stage2: switch ranges and multi item prongsVexu
2020-10-30stage2: disallow switching on floatsVexu
2020-10-30stage2: redesign switchbrVexu
2020-10-30stage2: switch emit zirVexu
2020-10-30stage2: basic switch analysisVexu
2020-10-30stage2: basic switch validationVexu
2020-10-30stage2: switch astgenVexu
2020-10-30stage2: detect import outside file pathVexu
2020-09-30stage2: struct type field accessVexu
2020-09-30stage2: very basic importsVexu
2020-09-30stage2: add import builtin stubVexu
2020-09-21rename src-self-hosted/ to src/Andrew Kelley