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path: root/src/zir.zig
AgeCommit message (Expand)Author
2021-01-19astgen: eliminate rlWrapPtr and all its callsitesAndrew Kelley
2021-01-18stage2: rework ZIR/TZIR for optionals and error unionsAndrew Kelley
2021-01-16stage2: implement error notes and regress -femit-zirAndrew Kelley
2021-01-11Merge branch 'Stage2 begin implementing container types'Andrew Kelley
2021-01-10stage2: add support for loops in LLVM backendTimon Kruiper
2021-01-09Merge pull request #7725 from FireFox317/even-more-llvmAndrew Kelley
2021-01-08stage2: implement TZIR printing for `block` and `condbr`Timon Kruiper
2021-01-07remove z/Z format specifiersJonathan Marler
2021-01-07Reduce use of deprecated IO typesJay Petacat
2021-01-05stage2: add compile log statementg-w1
2021-01-04stage2: improvements to `@setEvalBranchQuota`Andrew Kelley
2021-01-04stage2: implementation of `@setEvalBranchQuota`:g-w1
2021-01-02stage2: support recursive inline/comptime functionsAndrew Kelley
2021-01-02stage2: re-use ZIR for comptime and inline callsAndrew Kelley
2021-01-02stage2: implement function call inlining in the frontendAndrew Kelley
2021-01-02stage2: comptime function callsAndrew Kelley
2021-01-02convert more {} to {d} and {s}Andrew Kelley
2021-01-02stage2: Use {s} instead of {} when formatting stringsLemonBoy
2020-12-31stage2: inferred local variablesAndrew Kelley
2020-12-30stage2: rework Value Payload layoutAndrew Kelley
2020-12-30stage2: rework Type Payload layoutAndrew Kelley
2020-12-28Revert "stage2: add compile log statement (#7191)"Andrew Kelley
2020-12-28stage2: make Alloc(Inferred) have mutabality info (#7570)g-w1
2020-12-26make compileError use an UnOp since its operand is just a *Instg-w1
2020-12-26add test for @compileError in zig code, not only zirg-w1
2020-12-26change zir definition to use *Inst instead of []const u8g-w1
2020-12-26stage2: add compile log statement (#7191)g-w1
2020-12-23Merge pull request #7507 from joachimschmidt557/stage2-armVeikka Tuominen
2020-12-23stage2: @TypeOf (#7475)g-w1
2020-12-21stage2 ARM: implement basic binary bitwise operationsjoachimschmidt557
2020-12-03stage2: make sure to emit the ZIR instructions of exported functionsTimon Kruiper
2020-11-19Add builtin.Signedness, use it instead of is_signedTadeo Kondrak
2020-11-17stage2: initial container astgenVexu
2020-11-13stage2: add zir instructions for creating container typesVexu
2020-10-30stage2: switch liveness analysisVexu
2020-10-30stage2: switch comptime executionVexu
2020-10-30stage2: switch ranges and multi item prongsVexu
2020-10-30stage2: disallow switching on floatsVexu
2020-10-30stage2: redesign switchbrVexu
2020-10-30stage2: dump generated zir with --verbose-irVexu
2020-10-30stage2: switch emit zirVexu
2020-10-30stage2: basic switch analysisVexu
2020-10-30stage2: basic switch validationVexu
2020-10-30stage2: switch astgenVexu
2020-10-17std: remove renderStringLiteral in favor of std.fmt specifierVexu
2020-09-30stage2: add import builtin stubVexu
2020-09-21rename src-self-hosted/ to src/Andrew Kelley