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path: root/src/link/SpirV.zig
AgeCommit message (Expand)Author
2022-11-23spirv: assemblerRobin Voetter
2022-10-24link: add an explicit error set for flush() and flushModule()Andrew Kelley
2022-08-18std.Target gains ObjectFormat fieldAndrew Kelley
2022-04-20stage2: use indexes for Decl objectsAndrew Kelley
2022-04-17stage2: expose progress bar API to linker backendsAndrew Kelley
2022-02-16link: avoid double close on openPath errorAndrew Kelley
2022-01-28spirv: new moduleRobin Voetter
2022-01-28spirv: keep track of air & liveness so that it can be used in flush()Robin Voetter
2021-11-30allocgate: std Allocator interface refactorLee Cannon
2021-09-24Spelling corrections (#9833)Josh Soref
2021-07-20stage2: update LLVM backend to new AIR memory layoutAndrew Kelley
2021-07-20stage2: Air and Liveness are passed ephemerallyAndrew Kelley
2021-07-20stage2: first pass over Module.zig for AIR memory layoutAndrew Kelley
2021-06-21cleanups related to unused paramsAndrew Kelley
2021-06-21fix code broken from previous commitJacob G-W
2021-06-10zig fmtAndrew Kelley
2021-06-03Breaking hash map changes for 0.8.0Martin Wickham
2021-05-22SPIR-V: Make functions which always return a null result return void insteadRobin Voetter
2021-05-22SPIR-V: Generate locals at the start of a functionRobin Voetter
2021-05-22SPIR-V: Debug line info/source infoRobin Voetter
2021-05-22SPIR-V: DeclGen constructor/destructorRobin Voetter
2021-05-22SPIR-V: branchingRobin Voetter
2021-05-22SPIR-V: Split out genCmp from genBinOpRobin Voetter
2021-05-22SPIR-V: ResultId and Word aliases to improve code clarityRobin Voetter
2021-05-22SPIR-V: Put types in SPIRVModule, some general restructuringRobin Voetter
2021-05-17Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgenAndrew Kelley
2021-05-16SPIR-V: Some instructions + constant generation setupRobin Voetter
2021-05-16SPIR-V: Function parameter generationRobin Voetter
2021-05-16SPIR-V: Restructure codegen a bitRobin Voetter
2021-05-15Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgenAndrew Kelley
2021-05-14SPIR-V: Begin generating typesRobin Voetter
2021-04-28stage2: prepare for mainining Decl references to ZIR indexesAndrew Kelley
2021-04-28stage2: semaDecl properly analyzes the decl blockAndrew Kelley
2021-04-26stage2: rewire the frontend driver to whole-file-zirAndrew Kelley
2021-02-24zig fmt src/Andrew Kelley
2021-01-19SPIR-V: Use free list for result id generationRobin Voetter
2021-01-19SPIR-V: OpMemoryModel and basic capability generationRobin Voetter
2021-01-19SPIR-V: Make emitting binary more efficientRobin Voetter
2021-01-19SPIR-V: Add glsl450 and vulkan spir-v operating system definitionsRobin Voetter
2021-01-19SPIR-V: Linking and codegen setupRobin Voetter
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