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path: root/src/ir.zig
AgeCommit message (Expand)Author
2021-04-08stage2: Add .div to ir.ziggracefu
2021-04-01stage2: implement structs in the frontendAndrew Kelley
2021-03-31Sema: fix else case code generation for switchAndrew Kelley
2021-03-28stage2: implement sema for @errorToInt and @intToErrorjacob gw
2021-03-23stage2: fix while loopsAndrew Kelley
2021-03-18stage2: the code is compiling againAndrew Kelley
2021-03-17stage2: Module and Sema are compiling againAndrew Kelley
2021-03-17stage2: work through some compile errors in Module and SemaAndrew Kelley
2021-03-16stage2: *WIP*: rework ZIR memory layout; overhaul source locationsAndrew Kelley
2021-03-11stage2 tzir: Add wrapping integer arithmetic instructionsjoachimschmidt557
2021-03-02stage2 ARM: Implement basic integer multiplicationjoachimschmidt557
2021-02-25improve stage2 to allow catch at comptime:g-w1
2021-02-12stage2: more progress towards Module/astgen building with new mem layoutAndrew Kelley
2021-02-01stage2 cbe: implement switchbrVeikka Tuominen
2021-01-31astgen: rework labeled blocksAndrew Kelley
2021-01-31sema: after block gets peer type resolved, insert type coercionsAndrew Kelley
2021-01-31stage2: rework astgen result locationsAndrew Kelley
2021-01-18stage2: rework ZIR/TZIR for optionals and error unionsAndrew Kelley
2021-01-01std: have std.meta.fieldInfo take an enum rather than a stringdaurnimator
2020-12-31stage2: inferred local variablesAndrew Kelley
2020-12-21stage2 ARM: implement basic binary bitwise operationsjoachimschmidt557
2020-10-30stage2: switch comptime executionVexu
2020-10-30stage2: switch ranges and multi item prongsVexu
2020-10-30stage2: redesign switchbrVexu
2020-10-30stage2: switch emit zirVexu
2020-10-30stage2: basic switch analysisVexu
2020-09-21rename src-self-hosted/ to src/Andrew Kelley