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AgeCommit message (Expand)Author
2021-04-04LLVM sub-arch triple: remove TODO commentAndrew Kelley
2021-04-02stage2: progress towards basic structsAndrew Kelley
2021-04-02stage2 AArch64: Add ldrh and ldrb instructionsjoachimschmidt557
2021-03-31Merge pull request #8266 from ziglang/zir-memory-layoutAndrew Kelley
2021-03-31stage2 AArch64: implement strb and strhjoachimschmidt557
2021-03-28Merge remote-tracking branch 'origin/master' into zir-memory-layoutAndrew Kelley
2021-03-28stage2: implement sema for @errorToInt and @intToErrorjacob gw
2021-03-23stage2: handle void value in genRet in LLVM backendTimon Kruiper
2021-03-23stage2: rename fail to todo in LLVM backendTimon Kruiper
2021-03-22Fix getNot and add test casesLuuk de Gram
2021-03-22Implement more instructions for more control flow supportLuuk de Gram
2021-03-20stage2: restructure LLVM backendTimon Kruiper
2021-03-19llvm backend: use new srclocjacob gw
2021-03-18stage2: the code is compiling againAndrew Kelley
2021-03-18stage2: get Module and Sema compiling againAndrew Kelley
2021-03-17zld: use aarch64 for opcodesJakub Konka
2021-03-16stage2 llvm bindings: use correct type for LLVMBool for ABI compatTadeo Kondrak
2021-03-14stage2 llvm bindings: rename LLVMBool to BoolTadeo Kondrak
2021-03-08stage2: error union payload must also be a valid variable typeVeikka Tuominen
2021-03-08stage2 cbe: add error union and error union operationsjacob gw
2021-03-08stage2 cbe: non pointer optionalsVeikka Tuominen
2021-03-08stage2 cbe: errorsVeikka Tuominen
2021-03-08stage2 cbe: regular optional typesVeikka Tuominen
2021-03-08stage2 cbe: pointer like optionalsVeikka Tuominen
2021-03-06stage2: implement var argsVeikka Tuominen
2021-03-02stage2: add support for optionals in the LLVM backendTimon Kruiper
2021-02-24zig fmt src/Andrew Kelley
2021-02-24Merge remote-tracking branch 'origin/master' into ast-memory-layoutAndrew Kelley
2021-02-21Merge pull request #7960 from Luukdegram/wasm-externVeikka Tuominen
2021-02-16std: remove io.AutoIndentingStreamIsaac Freund
2021-02-09stage2 ARM: fix callee_preserved_regsjoachimschmidt557
2021-02-05Ensure function indices are correct and fix a memory leakLuuk de Gram
2021-02-05Create type declarations for extern functions and write the 'import' sectionLuuk de Gram
2021-02-01Merge pull request #7827 from Snektron/spirv-setupAndrew Kelley
2021-02-01Merge pull request #7895 from Luukdegram/wasm-control-flowAndrew Kelley
2021-02-01stage2: reimplement switchVeikka Tuominen
2021-02-01stage2 cbe: implement not and some bitwise opsVeikka Tuominen
2021-02-01stage2 cbe: implement switchbrVeikka Tuominen
2021-02-01stage2 cbe: block resultsVeikka Tuominen
2021-02-01stage2 cbe: condbr and breaksVeikka Tuominen
2021-02-01stage2 cbe: use AutoIndentingStreamVeikka Tuominen
2021-02-01stage2 cbe: loop instructionVeikka Tuominen
2021-01-26Add tests, fix locals that are created in blocks like loops, and handle all b...Luuk de Gram
2021-01-25Merge pull request #7846 from LemonBoy/filtertestAndrew Kelley
2021-01-24Nested conditions and loops supportLuuk de Gram
2021-01-23add LTO supportAndrew Kelley
2021-01-22std: Update `test ""` to `test` where it makes senseLemonBoy
2021-01-19SPIR-V: Use free list for result id generationRobin Voetter
2021-01-19SPIR-V: OpMemoryModel and basic capability generationRobin Voetter
2021-01-19SPIR-V: Make emitting binary more efficientRobin Voetter
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