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path: root/src/codegen/spirv.zig
AgeCommit message (Expand)Author
2021-10-21stage2: more division supportAndrew Kelley
2021-10-02Delete Module.Scope, move Block into SemaMartin Wickham
2021-10-02Remove my dumb "namespace decl" hackMartin Wickham
2021-09-24Spelling corrections (#9833)Josh Soref
2021-09-19Update all ensureCapacity calls to the relevant non-deprecated versionRyan Liptak
2021-07-20stage2: update LLVM backend to new AIR memory layoutAndrew Kelley
2021-07-20stage2: Air and Liveness are passed ephemerallyAndrew Kelley
2021-07-20stage2: first pass over Module.zig for AIR memory layoutAndrew Kelley
2021-07-20stage2: update Liveness, SPIR-V for new AIR memory layoutAndrew Kelley
2021-07-20stage2: rework AIR memory layoutAndrew Kelley
2021-07-12C backend: TypedefMap is now ArrayHashMapAndrew Kelley
2021-06-21std, src, doc, test: remove unused variablesJacob G-W
2021-06-10zig fmtAndrew Kelley
2021-06-03Breaking hash map changes for 0.8.0Martin Wickham
2021-05-22Merge pull request #8852 from Snektron/spirvAndrew Kelley
2021-05-22stage2: rename ir.zig to air.zigAndrew Kelley
2021-05-22SPIR-V: Make functions which always return a null result return void insteadRobin Voetter
2021-05-22SPIR-V: Generate locals at the start of a functionRobin Voetter
2021-05-22SPIR-V: Debug line info/source infoRobin Voetter
2021-05-22SPIR-V: DeclGen constructor/destructorRobin Voetter
2021-05-22SPIR-V: branchingRobin Voetter
2021-05-22SPIR-V: Pass source location to genType and genConstant for better error repo...Robin Voetter
2021-05-22SPIR-V: Preliminary alloc/store/load generationRobin Voetter
2021-05-22SPIR-V: Split out genCmp from genBinOpRobin Voetter
2021-05-22SPIR-V: Preliminary integer constant encodingRobin Voetter
2021-05-22SPIR-V: ResultId and Word aliases to improve code clarityRobin Voetter
2021-05-22SPIR-V: Put types in SPIRVModule, some general restructuringRobin Voetter
2021-05-22SPIR-V: Use Value.toFloat instead of switching on value tag when generating f...Robin Voetter
2021-05-17Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgenAndrew Kelley
2021-05-16SPIR-V: Unary not operationRobin Voetter
2021-05-16SPIR-V: bool binary operationsRobin Voetter
2021-05-16SPIR-V: comparison and equality operationsRobin Voetter
2021-05-16SPIR-V: More bitwise binary operationsRobin Voetter
2021-05-16SPIR-V: More binary operationsRobin Voetter
2021-05-16SPIR-V: genBinOp setupRobin Voetter
2021-05-16SPIR-V: Some initial floating point constant generationRobin Voetter
2021-05-16SPIR-V: Some instructions + constant generation setupRobin Voetter
2021-05-16SPIR-V: Function parameter generationRobin Voetter
2021-05-16SPIR-V: OpFunction/OpFunctionEnd generationRobin Voetter
2021-05-16SPIR-V: Proper floating point type generationRobin Voetter
2021-05-16SPIR-V: Function prototype generationRobin Voetter
2021-05-16SPIR-V: Compute backing integer bitsRobin Voetter
2021-05-16SPIR-V: Restructure codegen a bitRobin Voetter
2021-05-15Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgenAndrew Kelley
2021-05-14SPIR-V: Begin generating typesRobin Voetter
2021-02-24zig fmt src/Andrew Kelley
2021-01-19SPIR-V: Use free list for result id generationRobin Voetter
2021-01-19SPIR-V: OpMemoryModel and basic capability generationRobin Voetter
2021-01-19SPIR-V: Make emitting binary more efficientRobin Voetter
2021-01-19SPIR-V: Linking and codegen setupRobin Voetter
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