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Age	Commit message (Collapse)	Author
2021-05-09	stage2 ARM: Overhaul of genArmBinOp	joachimschmidt557

2021-05-09	Merge pull request #8474 from gracefuu/grace/encode-instruction	Andrew Kelley
	stage2 x86_64: encoding helpers, fix bugs
2021-04-25	stage2 register manager: Use an array instead of a hashmap for tracking	joachimschmidt557
	allocated registers
2021-04-17	stage2 codegen: Fix silent bug in reuseOperand	joachimschmidt557

2021-04-16	stage2 x86_64: fix incorrect comment in genX8664BinMath	gracefu
	Co-authored-by: joachimschmidt557 <joachim.schmidt557@outlook.com>
2021-04-16	stage2 x86_64: force 64 bit mode when loading address of GOT	gracefu
	Co-authored-by: joachimschmidt557 <joachim.schmidt557@outlook.com>
2021-04-16	stage2 x86_64: fix codegen ensureCapacity bug for function calls	gracefu
	Co-authored-by: joachimschmidt557 <joachim.schmidt557@outlook.com>
2021-04-16	stage2 x86_64: bugfix abi_size == 64 should be abi_size == 8	gracefu

2021-04-16	stage2 x86_64: try to fix RIP-relative offset to GOT for macho	gracefu

2021-04-16	stage2 x86_64: simplify inst encoder to a set of dumb helper fns	gracefu

2021-04-16	stage2 x86_64: implement integer mul	gracefu
	This was also an experiment to see if it were easier to implement a new feature when using the instruction encoder. Verdict: It's not that much easier, but I think it's certainly much more readable, because the description of the Instruction annotates what each field means. Right now, precise knowledge of x86_64 instructions is still required because things like when to set the 64-bit flag, how to read x86_64 instruction references, etc. are still not automatically done for you. In the future, this interface might make it sligtly easier to write an assembler for x86_64, by abstracting the bit-fiddling aspects of instruction encoding.
2021-04-16	stage2 x86_64: use abi size to determine 64-bit operation	gracefu
	From my very cursory reading, it seems that the register manager doesn't distinguish between registers that are physically the same but have different sizes. In that case, this means that during codegen, we can't rely on `reg.size()` when determining the width of the operations we have to perform. Instead, we must use some form of `ty.abiSize(self.target.*)` to determine the size of the type we're operating with. If this size is 64 bits, then we should enable 64-bit operation. This fixed a bug in the codegen for spilling instructions, which was overwriting the previous stack entry with zeroes. See the modified test case in this commit.
2021-04-16	stage2 x86_64: refactor codegen to use inst encoder	gracefu
	There are parts of it that I didn't modify because the byte representation was important (e.g. we need to know what the exact byte position where we store the address into the offset table is)
2021-04-11	stage2 ARM: Add fibonacci test	joachimschmidt557

2021-04-11	stage2 codegen: Set MCValue of register arguments to their stack copy	joachimschmidt557

2021-04-09	Merge pull request #8470 from ziglang/stage2-start	Andrew Kelley
	stage2: blaze the trail for std lib integration
2021-04-08	stage2: simplify Decl src_node field	Andrew Kelley
	Also fix "previous definition here" error notes to be correct.
2021-04-08	Merge pull request #8464 from gracefuu/grace/wasm-ops	Andrew Kelley
	stage2 wasm: Add division and bitwise/boolean ops &, \|, ^, and, or
2021-04-08	stage2: Add .div to ir.zig	gracefu

2021-04-07	stage2 regalloc: Add unit test for getReg	joachimschmidt557

2021-04-06	stage2 regalloc: Add getReg and getRegWithoutTracking	joachimschmidt557

2021-04-02	stage2 AArch64: Add ldrh and ldrb instructions	joachimschmidt557

2021-04-02	stage2 register_manager: Add unit tests for tryAllocReg and allocReg	joachimschmidt557

2021-04-02	stage2 codegen: Extract register management code into separate file	joachimschmidt557

2021-04-01	stage2: implement structs in the frontend	Andrew Kelley
	New ZIR instructions: * struct_decl_packed * struct_decl_extern New TZIR instruction: struct_field_ptr Introduce `Module.Struct`. It uses `Value` to store default values and abi alignments. Implemented Sema.analyzeStructFieldPtr and zirStructDecl. Some stuff I changed from `@panic("TODO")` to `log.warn("TODO")`. It's becoming more clear that we need the lazy value mechanism soon; Type is becoming unruly, and some of these functions have too much logic given that they don't have any context for memory management or error reporting.
2021-03-31	Merge pull request #8266 from ziglang/zir-memory-layout	Andrew Kelley
	rework ZIR memory layout; overhaul source locations
2021-03-31	Sema: implement switch validation for ranges	Andrew Kelley

2021-03-31	stage2 codegen: Make sure function return value is in a callee	joachimschmidt557
	preserved register
2021-03-31	stage2 AArch64: implement strb and strh	joachimschmidt557

2021-03-28	stage2: implement sema for @errorToInt and @intToError	jacob gw

2021-03-18	stage2: codegen: update asm IR to new names	Andrew Kelley

2021-03-18	stage2: the code is compiling again	Andrew Kelley
	(with a lot of things commented out)
2021-03-18	stage2: get Module and Sema compiling again	Andrew Kelley
	There are some `@panic("TODO")` in there but I'm trying to get the branch to the point where collaborators can jump in. Next is to repair the seam between LazySrcLoc and codegen's expected absolute file offsets.
2021-03-18	Merge remote-tracking branch 'origin/master' into zir-memory-layout	Andrew Kelley
	I need the enum arrays that were just merged into master.
2021-03-17	stage2: Module and Sema are compiling again	Andrew Kelley
	Next up is reworking the seam between the LazySrcLoc emitted by Sema and the byte offsets currently expected by codegen. And then the big one: updating astgen.zig to use the new memory layout.
2021-03-17	macho: offset table part of GOT	Jakub Konka

2021-03-17	macho: apply some renames to bring closer to zld	Jakub Konka

2021-03-11	Merge pull request #7934 from Vexu/stage2-cbe	Andrew Kelley
	Stage2 cbe: optionals and errors
2021-03-11	stage2 tzir: Add wrapping integer arithmetic instructions	joachimschmidt557

2021-03-08	cbe: add error comparison support	jacob gw

2021-03-02	stage2 ARM: Implement basic integer multiplication	joachimschmidt557

2021-02-25	improve stage2 to allow catch at comptime:	g-w1
	* add error_union value tag. * add analyzeIsErr * add Value.isError * add TZIR wrap_errunion_payload and wrap_errunion_err for wrapping from T -> E!T and E -> E!T * add anlyzeInstUnwrapErrCode and analyzeInstUnwrapErr * add analyzeInstEnsureErrPayloadVoid: * add wrapErrorUnion * add comptime error comparison for tests * tests!
2021-02-25	stage2 ARM: Save callee-saved registers	joachimschmidt557
	Add a new allocated_registers bitmap to keep track of all callee-saved registers allocated during generation of this function. Function(.arm).gen uses this data to generate instructions in the function prologue and epilogue to push and pop these registers respectively.
2021-02-24	zig fmt src/	Andrew Kelley

2021-02-24	Merge remote-tracking branch 'origin/master' into ast-memory-layout	Andrew Kelley

2021-02-21	stage2 codegen: Add Type argument to genSetReg	joachimschmidt557

2021-02-12	stage2: more progress towards Module/astgen building with new mem layout	Andrew Kelley

2021-02-12	stage2: fix zero-sized function parameters (#7998)	Tadeo Kondrak

2021-02-09	require specifier for arrayish types	Jonathan Marler

2021-02-09	stage2 ARM: fix register allocation in genArmBinOp	joachimschmidt557
	Previously, this would reuse an operand even if reuseOperand returned false for both operands. genArmBinOpCode was also changed to be more Three-address code oriented in the process.