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path: root/src/astgen.zig
AgeCommit message (Expand)Author
2020-12-28Revert "stage2: add compile log statement (#7191)"Andrew Kelley
2020-12-28stage2: make Alloc(Inferred) have mutabality info (#7570)g-w1
2020-12-26add test for @compileError in zig code, not only zirg-w1
2020-12-26Merge pull request #7552 from Vexu/stage2-continueVeikka Tuominen
2020-12-26stage2: add compile log statement (#7191)g-w1
2020-12-26stage2: add error for unused labelsVeikka Tuominen
2020-12-26stage2: break and continue out of loopsVeikka Tuominen
2020-12-23stage2: @TypeOf (#7475)g-w1
2020-12-06stage2: variable shadowing detection (#6969)g-w1
2020-10-30stage2: switch put swap condbr and blockVexu
2020-10-30stage2: switch comptime executionVexu
2020-10-30stage2: switch ranges and multi item prongsVexu
2020-10-30stage2: redesign switchbrVexu
2020-10-30stage2: switch emit zirVexu
2020-10-30stage2: basic switch analysisVexu
2020-10-30stage2: basic switch validationVexu
2020-10-30stage2: switch astgenVexu
2020-09-30stage2: add import builtin stubVexu
2020-09-21rename src-self-hosted/ to src/Andrew Kelley