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path: root/src/arch/x86_64/bits.zig
AgeCommit message (Expand)Author
2022-05-25x64: move from compare_flags_* mcv to eflags with condition codes enumJakub Konka
2022-05-20x64: implement matching SSE instructions for generic cross-comp targetJakub Konka
2022-05-19x64: re-enable incremental testsJakub Konka
2022-05-19x64: use register classes mask to select between gp and avxJakub Konka
2022-05-19x64: merge general purpose with simd register into one bitsetJakub Konka
2022-05-19x64: add vmovsd RM and MR lowerings (first draft)Jakub Konka
2022-05-19x64: clean up populating VEX prefixJakub Konka
2022-05-19x64: extend Emit to allow for AVX registersJakub Konka
2022-05-19x64: add AVX registers and Vex prefix sub-encoderJakub Konka
2022-03-11stage2 regalloc: replace Register.allocIndex with generic indexOfRegjoachimschmidt557
2021-11-19stage2,x86_64: revert fixing callee preserved regsJakub Konka
2021-11-19stage2,x86_64: fix genBinMathOp and clarify callee-saved regsJakub Konka
2021-11-19stage2 x86_64 codegen: don't count return registers as callee-preservedJacob G-W
2021-11-08stage2 x86_64: add MIR->Isel lowering step for x86_64Jakub Konka
2021-09-24stage2 codegen: move bit definitions to src/archjoachimschmidt557