| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2022-05-25 | x64: move from compare_flags_* mcv to eflags with condition codes enum | Jakub Konka | |
| 2022-05-24 | stage2: fixes for error unions, optionals, errors | Andrew Kelley | |
| * `?E` where E is an error set with only one field now lowers the same as `bool`. * Fix implementation of errUnionErrOffset and errUnionPayloadOffset to properly compute the offset of each field. Also name them the same as the corresponding LLVM functions and have the same function signature, to avoid confusion. This fixes a bug where wasm was passing the error union type instead of the payload type. * Fix C backend handling of optionals with zero-bit payload types. * C backend: separate out airOptionalPayload and airOptionalPayloadPtr which reduces branching and cleans up control flow. * Make Type.isNoReturn return true for error sets with no fields. * Make `?error{}` have only one possible value (null). | |||
| 2022-05-24 | aarch64: update for new error union layout | Jakub Konka | |
| 2022-05-24 | x64: update for new error union layout | Jakub Konka | |
| 2022-05-24 | dwarf: update abbrev info generation for new error union layout | Jakub Konka | |
| 2022-05-20 | x64: implement matching SSE instructions for generic cross-comp target | Jakub Konka | |
| 2022-05-19 | regalloc: make register class bitmask non-optional | Jakub Konka | |
| 2022-05-19 | x64: load float from memory to register on PIE targets | Jakub Konka | |
| 2022-05-19 | x64: check for floating-point intrinsics in codegen | Jakub Konka | |
| 2022-05-19 | x64: use StaticBitSet instead of an integer internally in RegisterManager | Jakub Konka | |
| 2022-05-19 | x64: re-enable behavior tests | Jakub Konka | |
| 2022-05-19 | x64: handle basic f32 using AVX registers | Jakub Konka | |
| 2022-05-19 | x64: remove special-casing of AVX for br() | Jakub Konka | |
| 2022-05-19 | x64: use register classes mask to select between gp and avx | Jakub Konka | |
| 2022-05-19 | regalloc: allow for optional selector mask when allocating | Jakub Konka | |
| 2022-05-19 | x64: merge general purpose with simd register into one bitset | Jakub Konka | |
| This way, we do not have to tweak the `RegisterManager` to handle multiple register types - we have one linear space instead. Additionally we can use the bitset itself to separate the registers into overlapping (the ones that are aliases of differing bitwidths) and nonoverlapping classes (for example, AVX registers do not overlap general purpose registers, thus they can be allocated simultaneously). Another huge benefit of this simple approach is the fact that we can still refer to *all* registers regardless of their class via enum literals which makes the code so much more readable. Finally, `RegisterLock` is universal across different register classes. | |||
| 2022-05-19 | x64: add unordered cmp with EFLAGS | Jakub Konka | |
| 2022-05-19 | x64: load/store to/from AVX registers for f64 | Jakub Konka | |
| 2022-05-17 | stage2: fix pointer arithmetic result type | Andrew Kelley | |
| This makes it so the result of doing pointer arithmetic creates a new pointer type that has adjusted alignment. | |||
| 2022-05-16 | stage2: disable error return tracing on unsupported targets | Veikka Tuominen | |
| 2022-05-16 | stage2: implement error return traces | Veikka Tuominen | |
| 2022-05-15 | x64: rename brk to int3, and MIR to interrupt | Jakub Konka | |
| 2022-05-15 | x64: remove verbose_mir functionality | Jakub Konka | |
| Originally I thought interleaving AIR with MIR will be useful, however as it stands, I have used it very sporadically, and recently, not at all, and I do not think anyone else is actually using it. If there is a simple error such as a wrong instruction emitted, `objdump` is perfectly capable of narrowing it down, while if there's something more subtle happening, regardless of having `--verbose-mir` functionality or not, you still gotta go via the debugger which offers a better view at interleaved source program with the emitted machine code. Finally, I believe `-femit-asm` when we add it will offer a more generic substitute. | |||
| 2022-05-10 | x64: fix binary not implementation | Jakub Konka | |
| 2022-05-10 | x64: implement shl with overflow for non-pow-2 | Jakub Konka | |
| 2022-05-10 | x64: implement shl_with_overflow for powers of two | Jakub Konka | |
| 2022-05-10 | x64: implement missing bits in add_with_overflow and sub_with_overflow | Jakub Konka | |
| 2022-05-10 | x64: implement shl_exact and shr_exact | Jakub Konka | |
| 2022-05-10 | x64: consolidate shifts into single MIR helper fn | Jakub Konka | |
| 2022-05-10 | x64: handle immediate as RHS of shift bin ops | Jakub Konka | |
| 2022-05-10 | x64: pull shl and shr into one helper fn | Jakub Konka | |
| 2022-05-10 | x64: refactor genMulDivBinOp helper | Jakub Konka | |
| 2022-05-10 | x64: migrate div to genMulDivBinOp | Jakub Konka | |
| 2022-05-10 | x64: converge add_with_overflow and sub_with_overflow | Jakub Konka | |
| 2022-05-10 | x64: make genBinOp operate on MCValues directly | Jakub Konka | |
| 2022-05-10 | x64: migrate mod and rem into genBinOp | Jakub Konka | |
| 2022-05-09 | x64: pass tag and maybe_inst explictly to genBinOp | Jakub Konka | |
| 2022-05-09 | x64: migrate mul to new genBinOp helper | Jakub Konka | |
| 2022-05-09 | x64: make one entry point for binary ops | Jakub Konka | |
| * rename `genBinMathOp` into `genBinOp` and handle commutativity * rename `genBinMathOpMir` into `genBinOpMir` | |||
| 2022-05-09 | x64: add naive impl of shr | Jakub Konka | |
| 2022-05-07 | regalloc: refactor locking multiple registers at once | Jakub Konka | |
| 2022-05-07 | x64: refactor code to avoid stage1 sema limitations | Jakub Konka | |
| 2022-05-07 | regalloc: rename freeze/unfreeze to lock/unlock registers | Jakub Konka | |
| 2022-05-07 | x64: fix misused register locks | Jakub Konka | |
| 2022-05-07 | regalloc: ensure we only freeze/unfreeze at the outermost scope | Jakub Konka | |
| This prevents a nasty type of bugs where we accidentally unfreeze a register that was frozen purposely in the outer scope, risking accidental realloc of a taken register. Fix CF flags spilling on aarch64 backend. | |||
| 2022-05-06 | x64: handle CF flags spilling in overflow calls | Jakub Konka | |
| Handle spilling of CF flags set with an overflow call. Add saving stack offset to memory. | |||
| 2022-05-05 | x64: mul_with_overflow: cannot reuse operand if not the result | Jakub Konka | |
| 2022-05-05 | x64: handle unsigned mul_with_overflow for non-pow-2 ints | Jakub Konka | |
| 2022-05-05 | x64: handle signed mul_with_overflow for non-pow-2 ints | Jakub Konka | |
| 2022-05-05 | x64: explicitly handle Vector vs Int types for overflow arith | Jakub Konka | |
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index : zig | |
| General-purpose programming language and toolchain for maintaining robust, optimal, and reusable software. https://ziglang.org |
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