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2022-05-13target: Rename sparcv9 -> sparc64Koakuma
Rename all references of sparcv9 to sparc64, to make Zig align more with other projects. Also, added new function to convert glibc arch name to Zig arch name, since it refers to the architecture as sparcv9. This is based on the suggestion by @kubkon in PR 11847. (https://github.com/ziglang/zig/pull/11487#pullrequestreview-963761757)
2022-05-05sparcv9: fix typo in def commentJakub Konka
2022-05-05stage2: sparcv9: Update Mir tag doc commentsKoakuma
2022-05-05stage2: sparcv9: Simplify debug info emission, remove unused formatsKoakuma
2022-05-05stage2: sparcv9: Add debug info generation for argsKoakuma
2022-05-05stage2: sparcv9: Remove dbg_arg instructionKoakuma
2022-05-05stage2: sparcv9: Simplify genLoad/genStoreKoakuma
2022-05-05stage2: sparcv9: Fix stack space accountingKoakuma
2022-05-05stage2: sparcv9: Pad branch delay slots with nopsKoakuma
2022-05-05stage2: sparcv9: Implement basic stack load/storesKoakuma
2022-05-05stage2: sparcv9: Implement jmpl loweringKoakuma
2022-05-02stage2: improve inline asm stage1 compatibilityAndrew Kelley
* outputs can have names and be referenced with template replacements the same as inputs. * fix print_air.zig not decoding correctly. * LLVM backend: use a table for template names for simplicity
2022-04-27add new builtin function `@tan`Andrew Kelley
The reason for having `@tan` is that we already have `@sin` and `@cos` because some targets have machine code instructions for them, but in the case that the implementation needs to go into compiler-rt, sin, cos, and tan all share a common dependency which includes a table of data. To avoid duplicating this table of data, we promote tan to become a builtin alongside sin and cos. ZIR: The tag enum is at capacity so this commit moves `field_call_bind_named` to be `extended`. I measured this as one of the least used tags in the zig codebase. Fix libc math suffix for `f32` being wrong in both stage1 and stage2. stage1: add missing libc prefix for float functions.
2022-04-20stage2: use indexes for Decl objectsAndrew Kelley
Rather than allocating Decl objects with an Allocator, we instead allocate them with a SegmentedList. This provides four advantages: * Stable memory so that one thread can access a Decl object while another thread allocates additional Decl objects from this list. * It allows us to use u32 indexes to reference Decl objects rather than pointers, saving memory in Type, Value, and dependency sets. * Using integers to reference Decl objects rather than pointers makes serialization trivial. * It provides a unique integer to be used for anonymous symbol names, avoiding multi-threaded contention on an atomic counter.
2022-04-15update self hosted sources to language changesVeikka Tuominen
2022-04-14stage2: sparcv9: Add cmp_lt_errors_len AIR inst & fix asm parsingKoakuma
2022-04-14stage2: sparcv9: Fix Tcc encodingKoakuma
2022-04-14stage2: sparcv9: Use regular structs to encode instructionsKoakuma
Currently packed structs still has endian-dependent behavior, so it results in code that is not portable across platforms (see also issue 10113).
2022-04-14stage2: sparcv9: Implement enough instruction to compile simple exesKoakuma
2022-04-14stage2: sparcv9: zig fmtKoakuma
2022-04-14stage2: sparcv9: Test failure error loggingFlandre Scarlet
2022-04-14stage2: sparcv9: implement basic instruction loweringKoakuma
2022-04-14stage2: sparcv9: Implement basic asm codegenKoakuma
2022-04-14stage2: sparcv9: Add breakpoint, ret, and calling mechanismKoakuma
2022-04-14stage2: sparcv9: Add placeholders to generate a minimal programKoakuma
2022-04-14stage2: sparcv9: Different formatting for genBodyKoakuma
2022-04-14stage2: sparcv9: implement dbgAdvancePCAndLineKoakuma
2022-04-14stage2: sparcv9: Adjust RegisterManager settingsKoakuma
2022-04-14stage2: sparcv9: Placeholder for Air instructions in genBodyKoakuma
2022-04-14stage2: sparcv9: Change ordering in Mir TagKoakuma
2022-04-14stage2: sparcv9: Implement basic prologue/epilogue Mir emissionKoakuma
2022-04-14stage2: sparcv9: Emit debug inst placeholderKoakuma
2022-04-14stage2: sparcv9: Mir extraData implementationKoakuma
2022-04-14stage2: sparcv9: Initial resolveCallingConventionValues implementationKoakuma
2022-04-14stage2: sparcv9: Add skeleton codegen impl and necessary fieldsKoakuma
2022-04-14stage2: sparcv9: Add some initial checks in codegenKoakuma
2022-03-19stage2 sparcv9: zig fmtKoakuma
2022-03-19stage2 sparcv9: Fix unused parameter errors in CodegenKoakuma
2022-03-19stage2 sparcv9: Add placeholder files and generate() functionKoakuma
Add placeholder files for Codegen, Emit, and Mir stages, complete with a placeholder implementation of generate() to make it able to be plugged in to the frontend. At the moment the implementation just panics, it'll be worked on incrementally later. Also, this registers the sparcv9 backend files into CMakeLists.txt.
2022-03-17stage2 sparcv9: Add param/return regs listKoakuma
2022-03-17stage2 sparcv9: Add encoder test and packed struct workaroundKoakuma
2022-03-16stage2 sparcv9: Fix branch format assertsKoakuma
2022-03-16stage2 sparcv9: Add list of preserved regsKoakuma
2022-03-16stage2 sparcv9: Reorder Format 4 wrappers tooKoakuma
2022-03-16stage2 sparcv9: cc -> ccrKoakuma
2022-03-16stage2 sparcv9: Reorder wrapper parameters to textual assembly orderKoakuma
2022-03-16stage2 sparcv9: Add Format 3 encoderKoakuma
2022-03-16stage2 sparcv9: Fix bitcast typosKoakuma
2022-03-16stage2 sparcv9: Minor parameter type changesKoakuma
Use the `Condition` type for 2b/2c and signed integer for 4b/4d.
2022-03-16stage2 sparcv9: Add Format 4 encoderFlandre Scarlet
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