| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2025-09-26 | compiler: move self-hosted backends from src/arch to src/codegen | Alex Rønne Petersen | |
| 2025-09-21 | Elf2: create a new linker from scratch | Jacob Young | |
| This iteration already has significantly better incremental support. Closes #24110 | |||
| 2025-06-12 | x86_64: remove air references from mir | Jacob Young | |
| 2025-06-12 | compiler: get most backends compiling again | mlugg | |
| As of this commit, every backend other than self-hosted Wasm and self-hosted SPIR-V compiles and (at least somewhat) functions again. Those two backends are currently disabled with panics. Note that `Zcu.Feature.separate_thread` is *not* enabled for the fixed backends. Avoiding linker references from codegen is a non-trivial task, and can be done after this branch. | |||
| 2024-03-01 | compiler: audit debug mode checks | Jacob Young | |
| * Introduce `-Ddebug-extensions` for enabling compiler debug helpers * Replace safety mode checks with `std.debug.runtime_safety` * Replace debugger helper checks with `!builtin.strip_debug_info` Sometimes, you just have to debug optimized compilers... | |||
| 2023-06-24 | all: migrate code to new cast builtin syntax | mlugg | |
| Most of this migration was performed automatically with `zig fmt`. There were a few exceptions which I had to manually fix: * `@alignCast` and `@addrSpaceCast` cannot be automatically rewritten * `@truncate`'s fixup is incorrect for vectors * Test cases are not formatted, and their error locations change | |||
| 2023-04-28 | stage2: sparc64: Implement airByteSwap | Koakuma | |
| 2022-12-17 | std.builtin: rename Type.UnionField and Type.StructField's field_type to type | r00ster91 | |
| 2022-09-14 | stage2: sparc64: Change branch_link Mir field definition | Koakuma | |
| 2022-09-13 | stage2: support being built in ReleaseSafe mode | Andrew Kelley | |
| 2022-06-24 | stage2: sparc64: Implement airRem, airMod, and SPARCv9 s/udivx | Koakuma | |
| 2022-06-24 | stage2: sparc64: Implement SPARCv9 shifts | Koakuma | |
| 2022-06-24 | stage2: sparc64: Implement airFence + SPARCv9 membar | Koakuma | |
| 2022-06-24 | stage2: sparc64: Implement airBinOp for and, or, and xor | Koakuma | |
| 2022-06-24 | stage2: sparc64: Use official encoding for `not rs2, rs1` | Koakuma | |
| 2022-06-24 | stage2: sparc64: Introduce condition_register MCValue type | Koakuma | |
| Introduce condition_register MCValue type for future uses with BPr/MOVr (mostly when needing to compare a signed value with zero) | |||
| 2022-06-06 | stage2: sparc64: Implement airNot | Koakuma | |
| 2022-06-06 | stage2: sparc64: Implement airAddSubOverflow | Koakuma | |
| 2022-06-06 | stage2: sparc64: Implement condition code spilling | Koakuma | |
| 2022-05-26 | stage2: sparc64: Add cmp and mov synthetic instructions | Koakuma | |
| 2022-05-16 | stage2: sparc64: Implement airSliceElemVal | Koakuma | |
| 2022-05-16 | stage2: sparc64: Implement airCmp | Koakuma | |
| 2022-05-16 | stage2: sparc64: Implement SPARCv9 bpr | Koakuma | |
| 2022-05-16 | stage2: sparc64: Split the conditionals between integer and FP ones | Koakuma | |
| On SPARCv9 the integer and FP conditional branch codes doesn't align with each other at all, so the two need to be treated separately. | |||
| 2022-05-16 | stage2: sparc64: Implement airIsErr and airIsNonErr | Koakuma | |
| 2022-05-13 | target: Rename sparcv9 -> sparc64 | Koakuma | |
| Rename all references of sparcv9 to sparc64, to make Zig align more with other projects. Also, added new function to convert glibc arch name to Zig arch name, since it refers to the architecture as sparcv9. This is based on the suggestion by @kubkon in PR 11847. (https://github.com/ziglang/zig/pull/11487#pullrequestreview-963761757) | |||
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index : zig | |
| General-purpose programming language and toolchain for maintaining robust, optimal, and reusable software. https://ziglang.org |
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