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path: root/src/arch/riscv64/Mir.zig
AgeCommit message (Expand)Author
2025-09-26compiler: move self-hosted backends from src/arch to src/codegenAlex Rønne Petersen
2025-09-21Elf2: create a new linker from scratchJacob Young
2025-08-29std.Io: delete GenericReaderAndrew Kelley
2025-07-07std.fmt: fully remove format string from format methodsAndrew Kelley
2025-07-07compiler: update a bunch of format stringsAndrew Kelley
2025-06-12x86_64: remove air references from mirJacob Young
2025-06-12compiler: get most backends compiling againmlugg
2024-07-26riscv: implement `lr/sr` loop logic for non-native atomicsDavid Rubin
2024-07-26riscv: clean up and unify encoding logicDavid Rubin
2024-07-26riscv: implement `@clz`David Rubin
2024-07-26riscv: un-cache the `avl` and `vtype` when returning from a function callDavid Rubin
2024-07-14riscv: vectors part 3David Rubin
2024-07-14riscv: vectors part 2David Rubin
2024-07-14riscv: vectors part 1David Rubin
2024-07-14riscv: implement `@fence`David Rubin
2024-07-14riscv: `@atomicRmw`David Rubin
2024-07-14riscv: `@atomicLoad` and `@atomicStore`David Rubin
2024-07-04compiler: type.zig -> Type.zigmlugg
2024-06-13riscv: rewrite "binOp"David Rubin
2024-06-13riscv: integer + float `@abs`David Rubin
2024-06-13riscv: implement more arithmetic instructionsDavid Rubin
2024-06-13riscv: first sign of floats!David Rubin
2024-06-13riscv: get basic libc interopDavid Rubin
2024-06-13riscv: switch progress + by-ref return progressDavid Rubin
2024-05-11riscv: by-value structs + `@min`David Rubin
2024-05-11riscv: math progressDavid Rubin
2024-05-11riscv: actually working test runnerDavid Rubin
2024-05-11riscv: big rewrite to use latest livenessDavid Rubin
2024-05-11riscv: add enough components to get a test runner workingDavid Rubin
2024-05-11riscv: implement `airNot`David Rubin
2024-05-11riscv: implement slicesDavid Rubin
2024-05-11riscv: totally rewrite how we do loads and storesDavid Rubin
2024-05-11riscv: implement a basic `@intCast`David Rubin
2024-05-11riscv: fix overflow checks in addition.David Rubin
2024-05-11riscv: add `allocReg` helper, and clean up some comparing logicDavid Rubin
2024-05-11riscv: pointer workDavid Rubin
2024-05-11riscv: reorganize `binOp` and implement `cmp_imm_gte` MIRDavid Rubin
2024-05-11riscv: 16 bit `@byteSwap`David Rubin
2024-05-11riscv: implement basic logical shiftingDavid Rubin
2024-05-11riscv: basic struct field accessDavid Rubin
2024-05-11riscv: implement basic branchingDavid Rubin
2024-05-11riscv: implement `@abs`David Rubin
2024-05-11riscv: basic function argumentsDavid Rubin
2024-05-11riscv: initial cleanup and workDavid Rubin
2024-03-01compiler: audit debug mode checksJacob Young
2023-06-24all: migrate code to new cast builtin syntaxmlugg
2023-03-04add @trap builtinr00ster91
2022-12-17std.builtin: rename Type.UnionField and Type.StructField's field_type to typer00ster91
2022-03-19stage2 RISCV64: implement add, sub for registersjoachimschmidt557
2022-03-19stage2 RISCV64: implement move register to registerjoachimschmidt557