zig - General-purpose programming language and toolchain for maintaining robust, optimal, and reusable software. https://ziglang.org

Age	Commit message (Collapse)	Author
2024-07-26	riscv: clean up and unify encoding logic	David Rubin

2024-07-26	riscv: implement `@clz`	David Rubin

2024-07-26	riscv: un-cache the `avl` and `vtype` when returning from a function call	David Rubin
	the csrs `avl` and `vtype` are considered caller-saved so it could have changed while inside of the function. the easiest way to handle this is to just set the cached `vtype` and `avl` to null, so that the next time something needs to set it, it'll emit an instruction instead of relying on a potentially invalid setting.
2024-07-14	riscv: vectors part 3	David Rubin

2024-07-14	riscv: vectors part 2	David Rubin

2024-07-14	riscv: vectors part 1	David Rubin

2024-07-14	riscv: implement `@fence`	David Rubin

2024-07-14	riscv: `@atomicRmw`	David Rubin
	Now we generate debug undefined constants when the user asks for them to dedup across the function decl. This takes 2 instructions instead of 7 in the RISC-V backend. TODO, we need to dedupe across function decl boundaries.
2024-07-14	riscv: `@atomicLoad` and `@atomicStore`	David Rubin

2024-06-13	riscv: rewrite "binOp"	David Rubin
	Reorganize how the binOp and genBinOp functions work. I've spent quite a while here reading exactly through the spec and so many tests are enabled because of several critical issues the old design had. There are some regressions that will take a long time to figure out individually so I will ignore them for now, and pray they get fixed by themselves. When we're closer to 100% passing is when I will start diving into them one-by-one.
2024-06-13	riscv: integer + float `@abs`	David Rubin

2024-06-13	riscv: implement more arithmetic instructions	David Rubin

2024-06-13	riscv: float args	David Rubin

2024-06-13	riscv: first sign of floats!	David Rubin

2024-06-13	riscv: `std.fmt.format` running	David Rubin
	- implements `airSlice`, `airBitAnd`, `airBitOr`, `airShr`. - got a basic design going for the `airErrorName` but for some reason it simply returns empty bytes. will investigate further. - only generating `.got.zig` entries when not compiling an object or shared library - reduced the total amount of ops a mnemonic can have to 3, simplifying the logic
2024-06-13	riscv: get basic libc interop	David Rubin

2024-06-13	riscv: switch progress + by-ref return progress	David Rubin

2024-05-11	riscv: by-value structs + `@min`	David Rubin

2024-05-11	riscv: math progress	David Rubin

2024-05-11	riscv: add stage2_riscv to test matrix and bypass failing tests	David Rubin

2024-05-11	riscv: actually working test runner	David Rubin

2024-05-11	riscv: back to hello world panics	David Rubin

2024-05-11	riscv: big rewrite to use latest liveness	David Rubin
	this one is even harder to document then the last large overhaul. TLDR; - split apart Emit.zig into an Emit.zig and a Lower.zig - created seperate files for the encoding, and now adding a new instruction is as simple as just adding it to a couple of switch statements and providing the encoding. - relocs are handled in a more sane maner, and we have a clear defining boundary between lea_symbol and load_symbol now. - a lot of different abstractions for things like the stack, memory, registers, and others. - we're using x86_64's FrameIndex now, which simplifies a lot of the tougher design process. - a lot more that I don't have the energy to document. at this point, just read the commit itself :p