zig - General-purpose programming language and toolchain for maintaining robust, optimal, and reusable software. https://ziglang.org

Age	Commit message (Collapse)	Author
2025-09-26	compiler: move self-hosted backends from src/arch to src/codegen	Alex Rønne Petersen

2025-09-21	Elf2: create a new linker from scratch	Jacob Young
	This iteration already has significantly better incremental support. Closes #24110
2025-08-28	compiler: update to not use GenericWriter	Andrew Kelley

2025-08-11	linker: delete plan9 support	Andrew Kelley
	This experimental target was never fully completed. The operating system is not that interesting or popular anyway, and the maintainer is no longer around. Not worth the maintenance burden. This code can be resurrected later if it is worth it. In such case it will be subject to greater scrutiny.
2025-07-07	compiler: fix a bunch of format strings	Andrew Kelley

2025-06-12	x86_64: remove linker references from codegen	Jacob Young

2025-01-15	switch to ArrayListUnmanaged for machine code	Andrew Kelley

2024-09-12	Replace deprecated default initializations with decl literals	Linus Groh

2024-09-10	codegen: implement output to the `.debug_info` section	Jacob Young

2024-08-21	elf: emit .rela.debug* sections for relocatable if required	Jakub Konka

2024-08-15	riscv: remove redundant by-symbol-name check; just check for PIC and extern ptr	Jakub Konka

2024-08-15	riscv: do not emit GOT relocations for special linker symbols	Jakub Konka

2024-08-13	fix compile errors in other codegen backends	Jakub Konka

2024-08-11	compiler: split Decl into Nav and Cau	mlugg
	The type `Zcu.Decl` in the compiler is problematic: over time it has gained many responsibilities. Every source declaration, container type, generic instantiation, and `@extern` has a `Decl`. The functions of these `Decl`s are in some cases entirely disjoint. After careful analysis, I determined that the two main responsibilities of `Decl` are as follows: * A `Decl` acts as the "subject" of semantic analysis at comptime. A single unit of analysis is either a runtime function body, or a `Decl`. It registers incremental dependencies, tracks analysis errors, etc. * A `Decl` acts as a "global variable": a pointer to it is consistent, and it may be lowered to a specific symbol by the codegen backend. This commit eliminates `Decl` and introduces new types to model these responsibilities: `Cau` (Comptime Analysis Unit) and `Nav` (Named Addressable Value). Every source declaration, and every container type requiring resolution (so not including `opaque`), has a `Cau`. For a source declaration, this `Cau` performs the resolution of its value. (When #131 is implemented, it is unsolved whether type and value resolution will share a `Cau` or have two distinct `Cau`s.) For a type, this `Cau` is the context in which type resolution occurs. Every non-`comptime` source declaration, every generic instantiation, and every distinct `extern` has a `Nav`. These are sent to codegen/link: the backends by definition do not care about `Cau`s. This commit has some minor technically-breaking changes surrounding `usingnamespace`. I don't think they'll impact anyone, since the changes are fixes around semantics which were previously inconsistent (the behavior changed depending on hashmap iteration order!). Aside from that, this changeset has no significant user-facing changes. Instead, it is an internal refactor which makes it easier to correctly model the responsibilities of different objects, particularly regarding incremental compilation. The performance impact should be negligible, but I will take measurements before merging this work into `master`. Co-authored-by: Jacob Young <jacobly0@users.noreply.github.com> Co-authored-by: Jakub Konka <kubkon@jakubkonka.com>
2024-08-07	elf: fix compile errors	Jakub Konka

2024-07-31	riscv: fix `.got` symbol loading	David Rubin

2024-07-26	riscv: implement basic tlv loads and stores	David Rubin

2024-07-26	riscv: clean up and unify encoding logic	David Rubin

2024-07-14	riscv: vectors part 2	David Rubin

2024-07-14	riscv: truncate `airStructFieldVal` result	David Rubin

2024-07-07	Zcu: introduce `PerThread` and pass to all the functions	Jacob Young

2024-06-13	riscv: `std.fmt.format` running	David Rubin
	- implements `airSlice`, `airBitAnd`, `airBitOr`, `airShr`. - got a basic design going for the `airErrorName` but for some reason it simply returns empty bytes. will investigate further. - only generating `.got.zig` entries when not compiling an object or shared library - reduced the total amount of ops a mnemonic can have to 3, simplifying the logic
2024-06-13	riscv: get basic libc interop	David Rubin

2024-05-11	riscv: back to hello world panics	David Rubin

2024-05-11	riscv: big rewrite to use latest liveness	David Rubin
	this one is even harder to document then the last large overhaul. TLDR; - split apart Emit.zig into an Emit.zig and a Lower.zig - created seperate files for the encoding, and now adding a new instruction is as simple as just adding it to a couple of switch statements and providing the encoding. - relocs are handled in a more sane maner, and we have a clear defining boundary between lea_symbol and load_symbol now. - a lot of different abstractions for things like the stack, memory, registers, and others. - we're using x86_64's FrameIndex now, which simplifies a lot of the tougher design process. - a lot more that I don't have the energy to document. at this point, just read the commit itself :p
2024-05-11	riscv: add enough components to get a test runner working	David Rubin

2024-05-11	riscv: implement `airNot`	David Rubin

2024-05-11	riscv: implement slices	David Rubin

2024-05-11	riscv: totally rewrite how we do loads and stores	David Rubin
	this commit is a little too large to document fully, however the main gist of it this - finish the `genInlineMemcpy` implement - rename `setValue` to `genCopy` as I agree with jacob that it's a better name - add in `genVarDbgInfo` for a better gdb experience - follow the x86_64's method for genCall, as the procedure is very similar for us - add `airSliceLen` as it's trivial - change up the `airAddWithOverflow implementation a bit - make sure to not spill of the elem_ty is 0 size - correctly follow the RISC-V calling convention and spill the used calle saved registers in the prologue and restore them in the epilogue - add `address`, `deref`, and `offset` helper functions for MCValue. I must say I love these, they make the code very readable and super verbose :) - fix a `register_manager.zig` issue where when using the last register in the set, the value would overflow at comptime. was happening because we were adding to `max_id` before subtracting from it.
2024-05-11	riscv: implement a basic `@intCast`	David Rubin
	the truncation panic logic is generated in Sema, so I don't need to roll anything of my own. I add all of the boilerplate for that detecting the truncation and it works in basic test cases!
2024-05-11	riscv: fix overflow checks in addition.	David Rubin

2024-05-11	riscv: change `load_symbol` psuedo instruction size to 8	David Rubin

2024-05-11	riscv: fix how we calculate stack offsets. allows for pass by reference ↵	David Rubin
	arguments.
2024-05-11	riscv: add `allocReg` helper, and clean up some comparing logic	David Rubin
	- Added the basic framework for panicing with an overflow in `airAddWithOverflow`, but there is no check done yet. - added the `cmp_lt`, `cmp_gte`, and `cmp_imm_eq` MIR instructions, and their respective functionality.
2024-05-11	riscv: pointer work	David Rubin
	lots of thinking later, ive begun to grasp my head around how the pointers should work. this commit allows basic pointer loading and storing to happen.
2024-05-11	riscv: reorganize `binOp` and implement `cmp_imm_gte` MIR	David Rubin
	this was an annoying one to do, as there is no (to my knowledge) myriad sequence that will allow us to do `gte` compares with an immediate without allocating a register. RISC-V provides a single instruction to do compares, that being `lt`, and so you need to use more than one for other variants, but in this case, i believe you need to allocate a register.
2024-05-11	riscv: 16 bit `@byteSwap`	David Rubin

2024-05-11	riscv: implement basic logical shifting	David Rubin

2024-05-11	riscv: add `cmp_eq` MIR instruction	David Rubin
	this opens up the door for addition!
2024-05-11	riscv: basic struct field access	David Rubin
	the current implementation only works when the struct is in a register. we use some shifting magic to get the field into the LSB, and from there, given the type provenance, the generated code should never reach into the bits beyond the bit size of the type and interact with the rest of the struct.
2024-05-11	riscv: implement basic branching	David Rubin
	we use a code offset map in Emit.zig to pre-compute what byte offset each MIR instruction is at. this is important because they can be of different size
2024-05-11	riscv: implement `@abs`	David Rubin
	- add the `abs` MIR instruction - implement `@abs` by shifting to the right by `bits - 1`, and xoring.
2024-05-11	riscv: update `start.zig` and restore ra from the proper stack offset	David Rubin

2024-05-11	riscv: basic function arguments	David Rubin
	- rename setRegOrMem -> setValue - a naive method of passing arguments by register - gather the prologue and epilogue and generate them in Emit.zig. this is cleaner because we have the final stack size in the emit step. - define the "fa" register set, which contains the RISC-V calling convention defined function argument registers
2024-05-11	riscv: initial cleanup and work	David Rubin

2024-01-01	fix a round of compile errors caused by this branch	Andrew Kelley

2023-10-05	plan9: refactor debug info	Jacob Young
	The main goal is to stop depending on `emit.lower.target`.
2023-06-24	all: migrate code to new cast builtin syntax	mlugg
	Most of this migration was performed automatically with `zig fmt`. There were a few exceptions which I had to manually fix: * `@alignCast` and `@addrSpaceCast` cannot be automatically rewritten * `@truncate`'s fixup is incorrect for vectors * Test cases are not formatted, and their error locations change
2023-03-04	add @trap builtin	r00ster91
	This introduces a new builtin function that compiles down to something that results in an illegal instruction exception/interrupt. It can be used to exit a program abnormally. This implements the builtin for all backends.
2023-02-18	update std lib and compiler sources to new for loop syntax	Andrew Kelley