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-rw-r--r--tools/update_cpu_features.zig113
1 files changed, 88 insertions, 25 deletions
diff --git a/tools/update_cpu_features.zig b/tools/update_cpu_features.zig
index 933d268e2b..3757b56743 100644
--- a/tools/update_cpu_features.zig
+++ b/tools/update_cpu_features.zig
@@ -51,25 +51,33 @@ const llvm_targets = [_]LlvmTarget{
.branch_quota = 2000,
.feature_overrides = &.{
.{
+ .llvm_name = "v8a",
+ .extra_deps = &.{ "fp_armv8", "neon" },
+ },
+ .{
.llvm_name = "CONTEXTIDREL2",
.zig_name = "contextidr_el2",
.desc = "Enable RW operand Context ID Register (EL2)",
},
.{
.llvm_name = "neoversee1",
- .zig_name = "neoverse_e1",
+ .flatten = true,
},
.{
.llvm_name = "neoversen1",
- .zig_name = "neoverse_n1",
+ .flatten = true,
},
.{
.llvm_name = "neoversen2",
- .zig_name = "neoverse_n2",
+ .flatten = true,
},
.{
.llvm_name = "neoversev1",
- .zig_name = "neoverse_v1",
+ .flatten = true,
+ },
+ .{
+ .llvm_name = "neoverse512tvb",
+ .flatten = true,
},
.{
.llvm_name = "exynosm3",
@@ -127,6 +135,10 @@ const llvm_targets = [_]LlvmTarget{
.flatten = true,
},
.{
+ .llvm_name = "apple-a7",
+ .flatten = true,
+ },
+ .{
.llvm_name = "apple-a10",
.flatten = true,
},
@@ -135,10 +147,22 @@ const llvm_targets = [_]LlvmTarget{
.flatten = true,
},
.{
+ .llvm_name = "apple-a12",
+ .flatten = true,
+ },
+ .{
+ .llvm_name = "apple-a13",
+ .flatten = true,
+ },
+ .{
.llvm_name = "apple-a14",
.flatten = true,
},
.{
+ .llvm_name = "apple-a7-sysreg",
+ .flatten = true,
+ },
+ .{
.llvm_name = "carmel",
.flatten = true,
},
@@ -151,6 +175,10 @@ const llvm_targets = [_]LlvmTarget{
.flatten = true,
},
.{
+ .llvm_name = "cortex-x2",
+ .flatten = true,
+ },
+ .{
.llvm_name = "falkor",
.flatten = true,
.extra_deps = &.{"v8a"},
@@ -196,12 +224,9 @@ const llvm_targets = [_]LlvmTarget{
.llvm_name = "tsv110",
.flatten = true,
},
- },
- .extra_features = &.{
.{
- .zig_name = "v8a",
- .desc = "Support ARM v8a instructions",
- .deps = &.{ "fp_armv8", "neon" },
+ .llvm_name = "ampere1",
+ .flatten = true,
},
},
.extra_cpus = &.{
@@ -310,6 +335,14 @@ const llvm_targets = [_]LlvmTarget{
.flatten = true,
},
.{
+ .llvm_name = "cortex-a710",
+ .flatten = true,
+ },
+ .{
+ .llvm_name = "cortex-x1c",
+ .flatten = true,
+ },
+ .{
.llvm_name = "r5",
.flatten = true,
},
@@ -543,6 +576,10 @@ const llvm_targets = [_]LlvmTarget{
.zig_name = "v8_7a",
},
.{
+ .llvm_name = "armv8.8-a",
+ .zig_name = "v8_8a",
+ },
+ .{
.llvm_name = "armv8-a",
.zig_name = "v8a",
},
@@ -559,6 +596,22 @@ const llvm_targets = [_]LlvmTarget{
.zig_name = "v8r",
},
.{
+ .llvm_name = "armv9.1-a",
+ .zig_name = "v9_1a",
+ },
+ .{
+ .llvm_name = "armv9.2-a",
+ .zig_name = "v9_2a",
+ },
+ .{
+ .llvm_name = "armv9.3-a",
+ .zig_name = "v9_3a",
+ },
+ .{
+ .llvm_name = "armv9-a",
+ .zig_name = "v9a",
+ },
+ .{
.llvm_name = "v4t",
.zig_name = "has_v4t",
},
@@ -638,6 +691,26 @@ const llvm_targets = [_]LlvmTarget{
.llvm_name = "v8.7a",
.zig_name = "has_v8_7a",
},
+ .{
+ .llvm_name = "v8.8a",
+ .zig_name = "has_v8_8a",
+ },
+ .{
+ .llvm_name = "v9a",
+ .zig_name = "has_v9a",
+ },
+ .{
+ .llvm_name = "v9.1a",
+ .zig_name = "has_v9_1a",
+ },
+ .{
+ .llvm_name = "v9.2a",
+ .zig_name = "has_v9_2a",
+ },
+ .{
+ .llvm_name = "v9.3a",
+ .zig_name = "has_v9_3a",
+ },
},
},
.{
@@ -695,6 +768,12 @@ const llvm_targets = [_]LlvmTarget{
.zig_name = "riscv",
.llvm_name = "RISCV",
.td_name = "RISCV.td",
+ .feature_overrides = &.{
+ .{
+ .llvm_name = "sifive7",
+ .flatten = true,
+ },
+ },
.extra_cpus = &.{
.{
.llvm_name = null,
@@ -738,22 +817,6 @@ const llvm_targets = [_]LlvmTarget{
.omit = true,
},
.{
- .llvm_name = "i386",
- .zig_name = "_i386",
- },
- .{
- .llvm_name = "i486",
- .zig_name = "_i486",
- },
- .{
- .llvm_name = "i586",
- .zig_name = "_i586",
- },
- .{
- .llvm_name = "i686",
- .zig_name = "_i686",
- },
- .{
.llvm_name = "lakemont",
.extra_deps = &.{"soft_float"},
},