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-rw-r--r--src/arch/x86_64/CodeGen.zig17
1 files changed, 17 insertions, 0 deletions
diff --git a/src/arch/x86_64/CodeGen.zig b/src/arch/x86_64/CodeGen.zig
index bdad8312d5..46682345b9 100644
--- a/src/arch/x86_64/CodeGen.zig
+++ b/src/arch/x86_64/CodeGen.zig
@@ -7177,6 +7177,23 @@ fn genBinOp(
dst_reg,
tmp_reg,
);
+ switch (air_tag) {
+ .div_trunc, .div_floor => try self.asmRegisterRegisterRegisterImmediate(
+ .{ .v_ss, .round },
+ dst_reg,
+ dst_reg,
+ dst_reg,
+ Immediate.u(@as(u5, @bitCast(RoundMode{
+ .mode = switch (air_tag) {
+ .div_trunc => .zero,
+ .div_floor => .down,
+ else => unreachable,
+ },
+ .precision = .inexact,
+ }))),
+ ),
+ else => {},
+ }
try self.asmRegisterRegisterImmediate(
.{ .v_, .cvtps2ph },
dst_reg,