aboutsummaryrefslogtreecommitdiff
path: root/src/codegen
diff options
context:
space:
mode:
Diffstat (limited to 'src/codegen')
-rw-r--r--src/codegen/aarch64.zig2
-rw-r--r--src/codegen/arm.zig125
-rw-r--r--src/codegen/c.zig1
-rw-r--r--src/codegen/llvm.zig169
-rw-r--r--src/codegen/llvm/bindings.zig278
-rw-r--r--src/codegen/riscv64.zig4
-rw-r--r--src/codegen/spirv/spec.zig4
-rw-r--r--src/codegen/x86.zig16
-rw-r--r--src/codegen/x86_64.zig34
9 files changed, 374 insertions, 259 deletions
diff --git a/src/codegen/aarch64.zig b/src/codegen/aarch64.zig
index 1c176df017..dfda04da85 100644
--- a/src/codegen/aarch64.zig
+++ b/src/codegen/aarch64.zig
@@ -52,7 +52,7 @@ pub const Register = enum(u6) {
}
pub fn dwarfLocOp(self: Register) u8 {
- return @as(u8, self.id()) + DW.OP_reg0;
+ return @as(u8, self.id()) + DW.OP.reg0;
}
};
diff --git a/src/codegen/arm.zig b/src/codegen/arm.zig
index d30479e1f1..ec9152f96b 100644
--- a/src/codegen/arm.zig
+++ b/src/codegen/arm.zig
@@ -170,7 +170,7 @@ pub const Register = enum(u5) {
}
pub fn dwarfLocOp(self: Register) u8 {
- return @as(u8, self.id()) + DW.OP_reg0;
+ return @as(u8, self.id()) + DW.OP.reg0;
}
};
@@ -192,7 +192,7 @@ pub const c_abi_int_return_regs = [_]Register{ .r0, .r1 };
/// Represents an instruction in the ARM instruction set architecture
pub const Instruction = union(enum) {
- DataProcessing: packed struct {
+ data_processing: packed struct {
// Note to self: The order of the fields top-to-bottom is
// right-to-left in the actual 32-bit int representation
op2: u12,
@@ -204,7 +204,7 @@ pub const Instruction = union(enum) {
fixed: u2 = 0b00,
cond: u4,
},
- Multiply: packed struct {
+ multiply: packed struct {
rn: u4,
fixed_1: u4 = 0b1001,
rm: u4,
@@ -215,7 +215,7 @@ pub const Instruction = union(enum) {
fixed_2: u6 = 0b000000,
cond: u4,
},
- MultiplyLong: packed struct {
+ multiply_long: packed struct {
rn: u4,
fixed_1: u4 = 0b1001,
rm: u4,
@@ -227,7 +227,17 @@ pub const Instruction = union(enum) {
fixed_2: u5 = 0b00001,
cond: u4,
},
- SingleDataTransfer: packed struct {
+ integer_saturating_arithmetic: packed struct {
+ rm: u4,
+ fixed_1: u8 = 0b0000_0101,
+ rd: u4,
+ rn: u4,
+ fixed_2: u1 = 0b0,
+ opc: u2,
+ fixed_3: u5 = 0b00010,
+ cond: u4,
+ },
+ single_data_transfer: packed struct {
offset: u12,
rd: u4,
rn: u4,
@@ -240,7 +250,7 @@ pub const Instruction = union(enum) {
fixed: u2 = 0b01,
cond: u4,
},
- ExtraLoadStore: packed struct {
+ extra_load_store: packed struct {
imm4l: u4,
fixed_1: u1 = 0b1,
op2: u2,
@@ -256,7 +266,7 @@ pub const Instruction = union(enum) {
fixed_3: u3 = 0b000,
cond: u4,
},
- BlockDataTransfer: packed struct {
+ block_data_transfer: packed struct {
register_list: u16,
rn: u4,
load_store: u1,
@@ -267,25 +277,25 @@ pub const Instruction = union(enum) {
fixed: u3 = 0b100,
cond: u4,
},
- Branch: packed struct {
+ branch: packed struct {
offset: u24,
link: u1,
fixed: u3 = 0b101,
cond: u4,
},
- BranchExchange: packed struct {
+ branch_exchange: packed struct {
rn: u4,
fixed_1: u1 = 0b1,
link: u1,
fixed_2: u22 = 0b0001_0010_1111_1111_1111_00,
cond: u4,
},
- SupervisorCall: packed struct {
+ supervisor_call: packed struct {
comment: u24,
fixed: u4 = 0b1111,
cond: u4,
},
- Breakpoint: packed struct {
+ breakpoint: packed struct {
imm4: u4,
fixed_1: u4 = 0b0111,
imm12: u12,
@@ -293,7 +303,7 @@ pub const Instruction = union(enum) {
},
/// Represents the possible operations which can be performed by a
- /// DataProcessing instruction
+ /// Data Processing instruction
const Opcode = enum(u4) {
// Rd := Op1 AND Op2
@"and",
@@ -530,16 +540,17 @@ pub const Instruction = union(enum) {
pub fn toU32(self: Instruction) u32 {
return switch (self) {
- .DataProcessing => |v| @bitCast(u32, v),
- .Multiply => |v| @bitCast(u32, v),
- .MultiplyLong => |v| @bitCast(u32, v),
- .SingleDataTransfer => |v| @bitCast(u32, v),
- .ExtraLoadStore => |v| @bitCast(u32, v),
- .BlockDataTransfer => |v| @bitCast(u32, v),
- .Branch => |v| @bitCast(u32, v),
- .BranchExchange => |v| @bitCast(u32, v),
- .SupervisorCall => |v| @bitCast(u32, v),
- .Breakpoint => |v| @intCast(u32, v.imm4) | (@intCast(u32, v.fixed_1) << 4) | (@intCast(u32, v.imm12) << 8) | (@intCast(u32, v.fixed_2_and_cond) << 20),
+ .data_processing => |v| @bitCast(u32, v),
+ .multiply => |v| @bitCast(u32, v),
+ .multiply_long => |v| @bitCast(u32, v),
+ .integer_saturating_arithmetic => |v| @bitCast(u32, v),
+ .single_data_transfer => |v| @bitCast(u32, v),
+ .extra_load_store => |v| @bitCast(u32, v),
+ .block_data_transfer => |v| @bitCast(u32, v),
+ .branch => |v| @bitCast(u32, v),
+ .branch_exchange => |v| @bitCast(u32, v),
+ .supervisor_call => |v| @bitCast(u32, v),
+ .breakpoint => |v| @intCast(u32, v.imm4) | (@intCast(u32, v.fixed_1) << 4) | (@intCast(u32, v.imm12) << 8) | (@intCast(u32, v.fixed_2_and_cond) << 20),
};
}
@@ -554,7 +565,7 @@ pub const Instruction = union(enum) {
op2: Operand,
) Instruction {
return Instruction{
- .DataProcessing = .{
+ .data_processing = .{
.cond = @enumToInt(cond),
.i = @boolToInt(op2 == .Immediate),
.opcode = @enumToInt(opcode),
@@ -573,7 +584,7 @@ pub const Instruction = union(enum) {
top: bool,
) Instruction {
return Instruction{
- .DataProcessing = .{
+ .data_processing = .{
.cond = @enumToInt(cond),
.i = 1,
.opcode = if (top) 0b1010 else 0b1000,
@@ -594,7 +605,7 @@ pub const Instruction = union(enum) {
ra: ?Register,
) Instruction {
return Instruction{
- .Multiply = .{
+ .multiply = .{
.cond = @enumToInt(cond),
.accumulate = @boolToInt(ra != null),
.set_cond = set_cond,
@@ -617,7 +628,7 @@ pub const Instruction = union(enum) {
rn: Register,
) Instruction {
return Instruction{
- .MultiplyLong = .{
+ .multiply_long = .{
.cond = @enumToInt(cond),
.unsigned = signed,
.accumulate = accumulate,
@@ -630,6 +641,24 @@ pub const Instruction = union(enum) {
};
}
+ fn integerSaturationArithmetic(
+ cond: Condition,
+ rd: Register,
+ rm: Register,
+ rn: Register,
+ opc: u2,
+ ) Instruction {
+ return Instruction{
+ .integer_saturating_arithmetic = .{
+ .rm = rm.id(),
+ .rd = rd.id(),
+ .rn = rn.id(),
+ .opc = opc,
+ .cond = @enumToInt(cond),
+ },
+ };
+ }
+
fn singleDataTransfer(
cond: Condition,
rd: Register,
@@ -642,7 +671,7 @@ pub const Instruction = union(enum) {
load_store: u1,
) Instruction {
return Instruction{
- .SingleDataTransfer = .{
+ .single_data_transfer = .{
.cond = @enumToInt(cond),
.rn = rn.id(),
.rd = rd.id(),
@@ -678,7 +707,7 @@ pub const Instruction = union(enum) {
};
return Instruction{
- .ExtraLoadStore = .{
+ .extra_load_store = .{
.imm4l = imm4l,
.op2 = op2,
.imm4h = imm4h,
@@ -705,7 +734,7 @@ pub const Instruction = union(enum) {
load_store: u1,
) Instruction {
return Instruction{
- .BlockDataTransfer = .{
+ .block_data_transfer = .{
.register_list = @bitCast(u16, reg_list),
.rn = rn.id(),
.load_store = load_store,
@@ -720,7 +749,7 @@ pub const Instruction = union(enum) {
fn branch(cond: Condition, offset: i26, link: u1) Instruction {
return Instruction{
- .Branch = .{
+ .branch = .{
.cond = @enumToInt(cond),
.link = link,
.offset = @bitCast(u24, @intCast(i24, offset >> 2)),
@@ -730,7 +759,7 @@ pub const Instruction = union(enum) {
fn branchExchange(cond: Condition, rn: Register, link: u1) Instruction {
return Instruction{
- .BranchExchange = .{
+ .branch_exchange = .{
.cond = @enumToInt(cond),
.link = link,
.rn = rn.id(),
@@ -740,7 +769,7 @@ pub const Instruction = union(enum) {
fn supervisorCall(cond: Condition, comment: u24) Instruction {
return Instruction{
- .SupervisorCall = .{
+ .supervisor_call = .{
.cond = @enumToInt(cond),
.comment = comment,
},
@@ -749,7 +778,7 @@ pub const Instruction = union(enum) {
fn breakpoint(imm: u16) Instruction {
return Instruction{
- .Breakpoint = .{
+ .breakpoint = .{
.imm12 = @truncate(u12, imm >> 4),
.imm4 = @truncate(u4, imm),
},
@@ -857,11 +886,11 @@ pub const Instruction = union(enum) {
return dataProcessing(cond, .mov, 1, rd, .r0, op2);
}
- pub fn bic(cond: Condition, rd: Register, op2: Operand) Instruction {
+ pub fn bic(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
return dataProcessing(cond, .bic, 0, rd, rn, op2);
}
- pub fn bics(cond: Condition, rd: Register, op2: Operand) Instruction {
+ pub fn bics(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
return dataProcessing(cond, .bic, 1, rd, rn, op2);
}
@@ -873,6 +902,24 @@ pub const Instruction = union(enum) {
return dataProcessing(cond, .mvn, 1, rd, .r0, op2);
}
+ // Integer Saturating Arithmetic
+
+ pub fn qadd(cond: Condition, rd: Register, rm: Register, rn: Register) Instruction {
+ return integerSaturationArithmetic(cond, rd, rm, rn, 0b00);
+ }
+
+ pub fn qsub(cond: Condition, rd: Register, rm: Register, rn: Register) Instruction {
+ return integerSaturationArithmetic(cond, rd, rm, rn, 0b01);
+ }
+
+ pub fn qdadd(cond: Condition, rd: Register, rm: Register, rn: Register) Instruction {
+ return integerSaturationArithmetic(cond, rd, rm, rn, 0b10);
+ }
+
+ pub fn qdsub(cond: Condition, rd: Register, rm: Register, rn: Register) Instruction {
+ return integerSaturationArithmetic(cond, rd, rm, rn, 0b11);
+ }
+
// movw and movt
pub fn movw(cond: Condition, rd: Register, imm: u16) Instruction {
@@ -887,7 +934,7 @@ pub const Instruction = union(enum) {
pub fn mrs(cond: Condition, rd: Register, psr: Psr) Instruction {
return Instruction{
- .DataProcessing = .{
+ .data_processing = .{
.cond = @enumToInt(cond),
.i = 0,
.opcode = if (psr == .spsr) 0b1010 else 0b1000,
@@ -901,7 +948,7 @@ pub const Instruction = union(enum) {
pub fn msr(cond: Condition, psr: Psr, op: Operand) Instruction {
return Instruction{
- .DataProcessing = .{
+ .data_processing = .{
.cond = @enumToInt(cond),
.i = 0,
.opcode = if (psr == .spsr) 0b1011 else 0b1001,
@@ -1294,6 +1341,10 @@ test "serialize instructions" {
.inst = Instruction.ldmea(.al, .r4, true, .{ .r2 = true, .r5 = true }),
.expected = 0b1110_100_1_0_0_1_1_0100_0000000000100100,
},
+ .{ // qadd r0, r7, r8
+ .inst = Instruction.qadd(.al, .r0, .r7, .r8),
+ .expected = 0b1110_00010_00_0_1000_0000_0000_0101_0111,
+ },
};
for (testcases) |case| {
diff --git a/src/codegen/c.zig b/src/codegen/c.zig
index 2084b1e1ce..fd964f2829 100644
--- a/src/codegen/c.zig
+++ b/src/codegen/c.zig
@@ -858,6 +858,7 @@ fn genBody(o: *Object, body: []const Air.Inst.Index) error{ AnalysisFail, OutOfM
// TODO use a different strategy for div that communicates to the optimizer
// that wrapping is UB.
.div => try airBinOp( o, inst, " / "),
+ .rem => try airBinOp( o, inst, " % "),
.cmp_eq => try airBinOp(o, inst, " == "),
.cmp_gt => try airBinOp(o, inst, " > "),
diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig
index d7aa2d45b3..8b7fd5dc54 100644
--- a/src/codegen/llvm.zig
+++ b/src/codegen/llvm.zig
@@ -167,7 +167,7 @@ pub const Object = struct {
const context = llvm.Context.create();
errdefer context.dispose();
- initializeLLVMTargets();
+ initializeLLVMTarget(options.target.cpu.arch);
const root_nameZ = try gpa.dupeZ(u8, options.root_name);
defer gpa.free(root_nameZ);
@@ -256,14 +256,6 @@ pub const Object = struct {
gpa.destroy(self);
}
- fn initializeLLVMTargets() void {
- llvm.initializeAllTargets();
- llvm.initializeAllTargetInfos();
- llvm.initializeAllTargetMCs();
- llvm.initializeAllAsmPrinters();
- llvm.initializeAllAsmParsers();
- }
-
fn locPath(
arena: *Allocator,
opt_loc: ?Compilation.EmitLoc,
@@ -796,11 +788,13 @@ pub const DeclGen = struct {
const gpa = self.gpa;
const elem_ty = tv.ty.elemType();
const elem_vals = payload.data;
- const llvm_elems = try gpa.alloc(*const llvm.Value, elem_vals.len);
+ const sento = tv.ty.sentinel();
+ const llvm_elems = try gpa.alloc(*const llvm.Value, elem_vals.len + @boolToInt(sento != null));
defer gpa.free(llvm_elems);
for (elem_vals) |elem_val, i| {
llvm_elems[i] = try self.genTypedValue(.{ .ty = elem_ty, .val = elem_val });
}
+ if (sento) |sent| llvm_elems[elem_vals.len] = try self.genTypedValue(.{ .ty = elem_ty, .val = sent });
const llvm_elem_ty = try self.llvmType(elem_ty);
return llvm_elem_ty.constArray(
llvm_elems.ptr,
@@ -985,6 +979,7 @@ pub const FuncGen = struct {
.mul => try self.airMul(inst, false),
.mulwrap => try self.airMul(inst, true),
.div => try self.airDiv(inst),
+ .rem => try self.airRem(inst),
.ptr_add => try self.airPtrAdd(inst),
.ptr_sub => try self.airPtrSub(inst),
@@ -1727,6 +1722,19 @@ pub const FuncGen = struct {
return self.builder.buildUDiv(lhs, rhs, "");
}
+ fn airRem(self: *FuncGen, inst: Air.Inst.Index) !?*const llvm.Value {
+ if (self.liveness.isUnused(inst)) return null;
+
+ const bin_op = self.air.instructions.items(.data)[inst].bin_op;
+ const lhs = try self.resolveInst(bin_op.lhs);
+ const rhs = try self.resolveInst(bin_op.rhs);
+ const inst_ty = self.air.typeOfIndex(inst);
+
+ if (inst_ty.isFloat()) return self.builder.buildFRem(lhs, rhs, "");
+ if (inst_ty.isSignedInt()) return self.builder.buildSRem(lhs, rhs, "");
+ return self.builder.buildURem(lhs, rhs, "");
+ }
+
fn airPtrAdd(self: *FuncGen, inst: Air.Inst.Index) !?*const llvm.Value {
if (self.liveness.isUnused(inst))
return null;
@@ -1957,3 +1965,144 @@ pub const FuncGen = struct {
return self.llvmModule().getIntrinsicDeclaration(id, null, 0);
}
};
+
+fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
+ switch (arch) {
+ .aarch64, .aarch64_be, .aarch64_32 => {
+ llvm.LLVMInitializeAArch64Target();
+ llvm.LLVMInitializeAArch64TargetInfo();
+ llvm.LLVMInitializeAArch64TargetMC();
+ llvm.LLVMInitializeAArch64AsmPrinter();
+ llvm.LLVMInitializeAArch64AsmParser();
+ },
+ .amdgcn => {
+ llvm.LLVMInitializeAMDGPUTarget();
+ llvm.LLVMInitializeAMDGPUTargetInfo();
+ llvm.LLVMInitializeAMDGPUTargetMC();
+ llvm.LLVMInitializeAMDGPUAsmPrinter();
+ llvm.LLVMInitializeAMDGPUAsmParser();
+ },
+ .arm, .armeb => {
+ llvm.LLVMInitializeARMTarget();
+ llvm.LLVMInitializeARMTargetInfo();
+ llvm.LLVMInitializeARMTargetMC();
+ llvm.LLVMInitializeARMAsmPrinter();
+ llvm.LLVMInitializeARMAsmParser();
+ },
+ .avr => {
+ llvm.LLVMInitializeAVRTarget();
+ llvm.LLVMInitializeAVRTargetInfo();
+ llvm.LLVMInitializeAVRTargetMC();
+ llvm.LLVMInitializeAVRAsmPrinter();
+ llvm.LLVMInitializeAVRAsmParser();
+ },
+ .bpfel, .bpfeb => {
+ llvm.LLVMInitializeBPFTarget();
+ llvm.LLVMInitializeBPFTargetInfo();
+ llvm.LLVMInitializeBPFTargetMC();
+ llvm.LLVMInitializeBPFAsmPrinter();
+ llvm.LLVMInitializeBPFAsmParser();
+ },
+ .hexagon => {
+ llvm.LLVMInitializeHexagonTarget();
+ llvm.LLVMInitializeHexagonTargetInfo();
+ llvm.LLVMInitializeHexagonTargetMC();
+ llvm.LLVMInitializeHexagonAsmPrinter();
+ llvm.LLVMInitializeHexagonAsmParser();
+ },
+ .lanai => {
+ llvm.LLVMInitializeLanaiTarget();
+ llvm.LLVMInitializeLanaiTargetInfo();
+ llvm.LLVMInitializeLanaiTargetMC();
+ llvm.LLVMInitializeLanaiAsmPrinter();
+ llvm.LLVMInitializeLanaiAsmParser();
+ },
+ .mips, .mipsel, .mips64, .mips64el => {
+ llvm.LLVMInitializeMipsTarget();
+ llvm.LLVMInitializeMipsTargetInfo();
+ llvm.LLVMInitializeMipsTargetMC();
+ llvm.LLVMInitializeMipsAsmPrinter();
+ llvm.LLVMInitializeMipsAsmParser();
+ },
+ .msp430 => {
+ llvm.LLVMInitializeMSP430Target();
+ llvm.LLVMInitializeMSP430TargetInfo();
+ llvm.LLVMInitializeMSP430TargetMC();
+ llvm.LLVMInitializeMSP430AsmPrinter();
+ llvm.LLVMInitializeMSP430AsmParser();
+ },
+ .nvptx, .nvptx64 => {
+ llvm.LLVMInitializeNVPTXTarget();
+ llvm.LLVMInitializeNVPTXTargetInfo();
+ llvm.LLVMInitializeNVPTXTargetMC();
+ llvm.LLVMInitializeNVPTXAsmPrinter();
+ // There is no LLVMInitializeNVPTXAsmParser function available.
+ },
+ .powerpc, .powerpcle, .powerpc64, .powerpc64le => {
+ llvm.LLVMInitializePowerPCTarget();
+ llvm.LLVMInitializePowerPCTargetInfo();
+ llvm.LLVMInitializePowerPCTargetMC();
+ llvm.LLVMInitializePowerPCAsmPrinter();
+ llvm.LLVMInitializePowerPCAsmParser();
+ },
+ .riscv32, .riscv64 => {
+ llvm.LLVMInitializeRISCVTarget();
+ llvm.LLVMInitializeRISCVTargetInfo();
+ llvm.LLVMInitializeRISCVTargetMC();
+ llvm.LLVMInitializeRISCVAsmPrinter();
+ llvm.LLVMInitializeRISCVAsmParser();
+ },
+ .sparc, .sparcv9, .sparcel => {
+ llvm.LLVMInitializeSparcTarget();
+ llvm.LLVMInitializeSparcTargetInfo();
+ llvm.LLVMInitializeSparcTargetMC();
+ llvm.LLVMInitializeSparcAsmPrinter();
+ llvm.LLVMInitializeSparcAsmParser();
+ },
+ .s390x => {
+ llvm.LLVMInitializeSystemZTarget();
+ llvm.LLVMInitializeSystemZTargetInfo();
+ llvm.LLVMInitializeSystemZTargetMC();
+ llvm.LLVMInitializeSystemZAsmPrinter();
+ llvm.LLVMInitializeSystemZAsmParser();
+ },
+ .wasm32, .wasm64 => {
+ llvm.LLVMInitializeWebAssemblyTarget();
+ llvm.LLVMInitializeWebAssemblyTargetInfo();
+ llvm.LLVMInitializeWebAssemblyTargetMC();
+ llvm.LLVMInitializeWebAssemblyAsmPrinter();
+ llvm.LLVMInitializeWebAssemblyAsmParser();
+ },
+ .i386, .x86_64 => {
+ llvm.LLVMInitializeX86Target();
+ llvm.LLVMInitializeX86TargetInfo();
+ llvm.LLVMInitializeX86TargetMC();
+ llvm.LLVMInitializeX86AsmPrinter();
+ llvm.LLVMInitializeX86AsmParser();
+ },
+ .xcore => {
+ llvm.LLVMInitializeXCoreTarget();
+ llvm.LLVMInitializeXCoreTargetInfo();
+ llvm.LLVMInitializeXCoreTargetMC();
+ llvm.LLVMInitializeXCoreAsmPrinter();
+ // There is no LLVMInitializeXCoreAsmParser function available.
+ },
+ .arc => {},
+ .csky => {},
+ .r600 => {},
+ .tce, .tcele => {},
+ .thumb, .thumbeb => {},
+ .le32, .le64 => {},
+ .amdil, .amdil64 => {},
+ .hsail, .hsail64 => {},
+ .spir, .spir64 => {},
+ .kalimba => {},
+ .shave => {},
+ .renderscript32 => {},
+ .renderscript64 => {},
+ .ve => {},
+ .spu_2 => {},
+ .spirv32 => {},
+ .spirv64 => {},
+ }
+}
diff --git a/src/codegen/llvm/bindings.zig b/src/codegen/llvm/bindings.zig
index d33ca29d4f..a10002b5d6 100644
--- a/src/codegen/llvm/bindings.zig
+++ b/src/codegen/llvm/bindings.zig
@@ -386,6 +386,15 @@ pub const Builder = opaque {
pub const buildFDiv = LLVMBuildFDiv;
extern fn LLVMBuildFDiv(*const Builder, LHS: *const Value, RHS: *const Value, Name: [*:0]const u8) *const Value;
+ pub const buildURem = LLVMBuildURem;
+ extern fn LLVMBuildURem(*const Builder, LHS: *const Value, RHS: *const Value, Name: [*:0]const u8) *const Value;
+
+ pub const buildSRem = LLVMBuildSRem;
+ extern fn LLVMBuildSRem(*const Builder, LHS: *const Value, RHS: *const Value, Name: [*:0]const u8) *const Value;
+
+ pub const buildFRem = LLVMBuildFRem;
+ extern fn LLVMBuildFRem(*const Builder, LHS: *const Value, RHS: *const Value, Name: [*:0]const u8) *const Value;
+
pub const buildAnd = LLVMBuildAnd;
extern fn LLVMBuildAnd(*const Builder, LHS: *const Value, RHS: *const Value, Name: [*:0]const u8) *const Value;
@@ -596,188 +605,93 @@ pub const Target = opaque {
extern fn LLVMGetTargetFromTriple(Triple: [*:0]const u8, T: **const Target, ErrorMessage: *[*:0]const u8) Bool;
};
-extern fn LLVMInitializeAArch64TargetInfo() void;
-extern fn LLVMInitializeAMDGPUTargetInfo() void;
-extern fn LLVMInitializeARMTargetInfo() void;
-extern fn LLVMInitializeAVRTargetInfo() void;
-extern fn LLVMInitializeBPFTargetInfo() void;
-extern fn LLVMInitializeHexagonTargetInfo() void;
-extern fn LLVMInitializeLanaiTargetInfo() void;
-extern fn LLVMInitializeMipsTargetInfo() void;
-extern fn LLVMInitializeMSP430TargetInfo() void;
-extern fn LLVMInitializeNVPTXTargetInfo() void;
-extern fn LLVMInitializePowerPCTargetInfo() void;
-extern fn LLVMInitializeRISCVTargetInfo() void;
-extern fn LLVMInitializeSparcTargetInfo() void;
-extern fn LLVMInitializeSystemZTargetInfo() void;
-extern fn LLVMInitializeWebAssemblyTargetInfo() void;
-extern fn LLVMInitializeX86TargetInfo() void;
-extern fn LLVMInitializeXCoreTargetInfo() void;
-extern fn LLVMInitializeAArch64Target() void;
-extern fn LLVMInitializeAMDGPUTarget() void;
-extern fn LLVMInitializeARMTarget() void;
-extern fn LLVMInitializeAVRTarget() void;
-extern fn LLVMInitializeBPFTarget() void;
-extern fn LLVMInitializeHexagonTarget() void;
-extern fn LLVMInitializeLanaiTarget() void;
-extern fn LLVMInitializeMipsTarget() void;
-extern fn LLVMInitializeMSP430Target() void;
-extern fn LLVMInitializeNVPTXTarget() void;
-extern fn LLVMInitializePowerPCTarget() void;
-extern fn LLVMInitializeRISCVTarget() void;
-extern fn LLVMInitializeSparcTarget() void;
-extern fn LLVMInitializeSystemZTarget() void;
-extern fn LLVMInitializeWebAssemblyTarget() void;
-extern fn LLVMInitializeX86Target() void;
-extern fn LLVMInitializeXCoreTarget() void;
-extern fn LLVMInitializeAArch64TargetMC() void;
-extern fn LLVMInitializeAMDGPUTargetMC() void;
-extern fn LLVMInitializeARMTargetMC() void;
-extern fn LLVMInitializeAVRTargetMC() void;
-extern fn LLVMInitializeBPFTargetMC() void;
-extern fn LLVMInitializeHexagonTargetMC() void;
-extern fn LLVMInitializeLanaiTargetMC() void;
-extern fn LLVMInitializeMipsTargetMC() void;
-extern fn LLVMInitializeMSP430TargetMC() void;
-extern fn LLVMInitializeNVPTXTargetMC() void;
-extern fn LLVMInitializePowerPCTargetMC() void;
-extern fn LLVMInitializeRISCVTargetMC() void;
-extern fn LLVMInitializeSparcTargetMC() void;
-extern fn LLVMInitializeSystemZTargetMC() void;
-extern fn LLVMInitializeWebAssemblyTargetMC() void;
-extern fn LLVMInitializeX86TargetMC() void;
-extern fn LLVMInitializeXCoreTargetMC() void;
-extern fn LLVMInitializeAArch64AsmPrinter() void;
-extern fn LLVMInitializeAMDGPUAsmPrinter() void;
-extern fn LLVMInitializeARMAsmPrinter() void;
-extern fn LLVMInitializeAVRAsmPrinter() void;
-extern fn LLVMInitializeBPFAsmPrinter() void;
-extern fn LLVMInitializeHexagonAsmPrinter() void;
-extern fn LLVMInitializeLanaiAsmPrinter() void;
-extern fn LLVMInitializeMipsAsmPrinter() void;
-extern fn LLVMInitializeMSP430AsmPrinter() void;
-extern fn LLVMInitializeNVPTXAsmPrinter() void;
-extern fn LLVMInitializePowerPCAsmPrinter() void;
-extern fn LLVMInitializeRISCVAsmPrinter() void;
-extern fn LLVMInitializeSparcAsmPrinter() void;
-extern fn LLVMInitializeSystemZAsmPrinter() void;
-extern fn LLVMInitializeWebAssemblyAsmPrinter() void;
-extern fn LLVMInitializeX86AsmPrinter() void;
-extern fn LLVMInitializeXCoreAsmPrinter() void;
-extern fn LLVMInitializeAArch64AsmParser() void;
-extern fn LLVMInitializeAMDGPUAsmParser() void;
-extern fn LLVMInitializeARMAsmParser() void;
-extern fn LLVMInitializeAVRAsmParser() void;
-extern fn LLVMInitializeBPFAsmParser() void;
-extern fn LLVMInitializeHexagonAsmParser() void;
-extern fn LLVMInitializeLanaiAsmParser() void;
-extern fn LLVMInitializeMipsAsmParser() void;
-extern fn LLVMInitializeMSP430AsmParser() void;
-extern fn LLVMInitializePowerPCAsmParser() void;
-extern fn LLVMInitializeRISCVAsmParser() void;
-extern fn LLVMInitializeSparcAsmParser() void;
-extern fn LLVMInitializeSystemZAsmParser() void;
-extern fn LLVMInitializeWebAssemblyAsmParser() void;
-extern fn LLVMInitializeX86AsmParser() void;
-
-pub const initializeAllTargetInfos = LLVMInitializeAllTargetInfos;
-fn LLVMInitializeAllTargetInfos() callconv(.C) void {
- LLVMInitializeAArch64TargetInfo();
- LLVMInitializeAMDGPUTargetInfo();
- LLVMInitializeARMTargetInfo();
- LLVMInitializeAVRTargetInfo();
- LLVMInitializeBPFTargetInfo();
- LLVMInitializeHexagonTargetInfo();
- LLVMInitializeLanaiTargetInfo();
- LLVMInitializeMipsTargetInfo();
- LLVMInitializeMSP430TargetInfo();
- LLVMInitializeNVPTXTargetInfo();
- LLVMInitializePowerPCTargetInfo();
- LLVMInitializeRISCVTargetInfo();
- LLVMInitializeSparcTargetInfo();
- LLVMInitializeSystemZTargetInfo();
- LLVMInitializeWebAssemblyTargetInfo();
- LLVMInitializeX86TargetInfo();
- LLVMInitializeXCoreTargetInfo();
-}
-pub const initializeAllTargets = LLVMInitializeAllTargets;
-fn LLVMInitializeAllTargets() callconv(.C) void {
- LLVMInitializeAArch64Target();
- LLVMInitializeAMDGPUTarget();
- LLVMInitializeARMTarget();
- LLVMInitializeAVRTarget();
- LLVMInitializeBPFTarget();
- LLVMInitializeHexagonTarget();
- LLVMInitializeLanaiTarget();
- LLVMInitializeMipsTarget();
- LLVMInitializeMSP430Target();
- LLVMInitializeNVPTXTarget();
- LLVMInitializePowerPCTarget();
- LLVMInitializeRISCVTarget();
- LLVMInitializeSparcTarget();
- LLVMInitializeSystemZTarget();
- LLVMInitializeWebAssemblyTarget();
- LLVMInitializeX86Target();
- LLVMInitializeXCoreTarget();
-}
-pub const initializeAllTargetMCs = LLVMInitializeAllTargetMCs;
-fn LLVMInitializeAllTargetMCs() callconv(.C) void {
- LLVMInitializeAArch64TargetMC();
- LLVMInitializeAMDGPUTargetMC();
- LLVMInitializeARMTargetMC();
- LLVMInitializeAVRTargetMC();
- LLVMInitializeBPFTargetMC();
- LLVMInitializeHexagonTargetMC();
- LLVMInitializeLanaiTargetMC();
- LLVMInitializeMipsTargetMC();
- LLVMInitializeMSP430TargetMC();
- LLVMInitializeNVPTXTargetMC();
- LLVMInitializePowerPCTargetMC();
- LLVMInitializeRISCVTargetMC();
- LLVMInitializeSparcTargetMC();
- LLVMInitializeSystemZTargetMC();
- LLVMInitializeWebAssemblyTargetMC();
- LLVMInitializeX86TargetMC();
- LLVMInitializeXCoreTargetMC();
-}
-pub const initializeAllAsmPrinters = LLVMInitializeAllAsmPrinters;
-fn LLVMInitializeAllAsmPrinters() callconv(.C) void {
- LLVMInitializeAArch64AsmPrinter();
- LLVMInitializeAMDGPUAsmPrinter();
- LLVMInitializeARMAsmPrinter();
- LLVMInitializeAVRAsmPrinter();
- LLVMInitializeBPFAsmPrinter();
- LLVMInitializeHexagonAsmPrinter();
- LLVMInitializeLanaiAsmPrinter();
- LLVMInitializeMipsAsmPrinter();
- LLVMInitializeMSP430AsmPrinter();
- LLVMInitializeNVPTXAsmPrinter();
- LLVMInitializePowerPCAsmPrinter();
- LLVMInitializeRISCVAsmPrinter();
- LLVMInitializeSparcAsmPrinter();
- LLVMInitializeSystemZAsmPrinter();
- LLVMInitializeWebAssemblyAsmPrinter();
- LLVMInitializeX86AsmPrinter();
- LLVMInitializeXCoreAsmPrinter();
-}
-pub const initializeAllAsmParsers = LLVMInitializeAllAsmParsers;
-fn LLVMInitializeAllAsmParsers() callconv(.C) void {
- LLVMInitializeAArch64AsmParser();
- LLVMInitializeAMDGPUAsmParser();
- LLVMInitializeARMAsmParser();
- LLVMInitializeAVRAsmParser();
- LLVMInitializeBPFAsmParser();
- LLVMInitializeHexagonAsmParser();
- LLVMInitializeLanaiAsmParser();
- LLVMInitializeMipsAsmParser();
- LLVMInitializeMSP430AsmParser();
- LLVMInitializePowerPCAsmParser();
- LLVMInitializeRISCVAsmParser();
- LLVMInitializeSparcAsmParser();
- LLVMInitializeSystemZAsmParser();
- LLVMInitializeWebAssemblyAsmParser();
- LLVMInitializeX86AsmParser();
-}
+pub extern fn LLVMInitializeAArch64TargetInfo() void;
+pub extern fn LLVMInitializeAMDGPUTargetInfo() void;
+pub extern fn LLVMInitializeARMTargetInfo() void;
+pub extern fn LLVMInitializeAVRTargetInfo() void;
+pub extern fn LLVMInitializeBPFTargetInfo() void;
+pub extern fn LLVMInitializeHexagonTargetInfo() void;
+pub extern fn LLVMInitializeLanaiTargetInfo() void;
+pub extern fn LLVMInitializeMipsTargetInfo() void;
+pub extern fn LLVMInitializeMSP430TargetInfo() void;
+pub extern fn LLVMInitializeNVPTXTargetInfo() void;
+pub extern fn LLVMInitializePowerPCTargetInfo() void;
+pub extern fn LLVMInitializeRISCVTargetInfo() void;
+pub extern fn LLVMInitializeSparcTargetInfo() void;
+pub extern fn LLVMInitializeSystemZTargetInfo() void;
+pub extern fn LLVMInitializeWebAssemblyTargetInfo() void;
+pub extern fn LLVMInitializeX86TargetInfo() void;
+pub extern fn LLVMInitializeXCoreTargetInfo() void;
+
+pub extern fn LLVMInitializeAArch64Target() void;
+pub extern fn LLVMInitializeAMDGPUTarget() void;
+pub extern fn LLVMInitializeARMTarget() void;
+pub extern fn LLVMInitializeAVRTarget() void;
+pub extern fn LLVMInitializeBPFTarget() void;
+pub extern fn LLVMInitializeHexagonTarget() void;
+pub extern fn LLVMInitializeLanaiTarget() void;
+pub extern fn LLVMInitializeMipsTarget() void;
+pub extern fn LLVMInitializeMSP430Target() void;
+pub extern fn LLVMInitializeNVPTXTarget() void;
+pub extern fn LLVMInitializePowerPCTarget() void;
+pub extern fn LLVMInitializeRISCVTarget() void;
+pub extern fn LLVMInitializeSparcTarget() void;
+pub extern fn LLVMInitializeSystemZTarget() void;
+pub extern fn LLVMInitializeWebAssemblyTarget() void;
+pub extern fn LLVMInitializeX86Target() void;
+pub extern fn LLVMInitializeXCoreTarget() void;
+
+pub extern fn LLVMInitializeAArch64TargetMC() void;
+pub extern fn LLVMInitializeAMDGPUTargetMC() void;
+pub extern fn LLVMInitializeARMTargetMC() void;
+pub extern fn LLVMInitializeAVRTargetMC() void;
+pub extern fn LLVMInitializeBPFTargetMC() void;
+pub extern fn LLVMInitializeHexagonTargetMC() void;
+pub extern fn LLVMInitializeLanaiTargetMC() void;
+pub extern fn LLVMInitializeMipsTargetMC() void;
+pub extern fn LLVMInitializeMSP430TargetMC() void;
+pub extern fn LLVMInitializeNVPTXTargetMC() void;
+pub extern fn LLVMInitializePowerPCTargetMC() void;
+pub extern fn LLVMInitializeRISCVTargetMC() void;
+pub extern fn LLVMInitializeSparcTargetMC() void;
+pub extern fn LLVMInitializeSystemZTargetMC() void;
+pub extern fn LLVMInitializeWebAssemblyTargetMC() void;
+pub extern fn LLVMInitializeX86TargetMC() void;
+pub extern fn LLVMInitializeXCoreTargetMC() void;
+
+pub extern fn LLVMInitializeAArch64AsmPrinter() void;
+pub extern fn LLVMInitializeAMDGPUAsmPrinter() void;
+pub extern fn LLVMInitializeARMAsmPrinter() void;
+pub extern fn LLVMInitializeAVRAsmPrinter() void;
+pub extern fn LLVMInitializeBPFAsmPrinter() void;
+pub extern fn LLVMInitializeHexagonAsmPrinter() void;
+pub extern fn LLVMInitializeLanaiAsmPrinter() void;
+pub extern fn LLVMInitializeMipsAsmPrinter() void;
+pub extern fn LLVMInitializeMSP430AsmPrinter() void;
+pub extern fn LLVMInitializeNVPTXAsmPrinter() void;
+pub extern fn LLVMInitializePowerPCAsmPrinter() void;
+pub extern fn LLVMInitializeRISCVAsmPrinter() void;
+pub extern fn LLVMInitializeSparcAsmPrinter() void;
+pub extern fn LLVMInitializeSystemZAsmPrinter() void;
+pub extern fn LLVMInitializeWebAssemblyAsmPrinter() void;
+pub extern fn LLVMInitializeX86AsmPrinter() void;
+pub extern fn LLVMInitializeXCoreAsmPrinter() void;
+
+pub extern fn LLVMInitializeAArch64AsmParser() void;
+pub extern fn LLVMInitializeAMDGPUAsmParser() void;
+pub extern fn LLVMInitializeARMAsmParser() void;
+pub extern fn LLVMInitializeAVRAsmParser() void;
+pub extern fn LLVMInitializeBPFAsmParser() void;
+pub extern fn LLVMInitializeHexagonAsmParser() void;
+pub extern fn LLVMInitializeLanaiAsmParser() void;
+pub extern fn LLVMInitializeMipsAsmParser() void;
+pub extern fn LLVMInitializeMSP430AsmParser() void;
+pub extern fn LLVMInitializePowerPCAsmParser() void;
+pub extern fn LLVMInitializeRISCVAsmParser() void;
+pub extern fn LLVMInitializeSparcAsmParser() void;
+pub extern fn LLVMInitializeSystemZAsmParser() void;
+pub extern fn LLVMInitializeWebAssemblyAsmParser() void;
+pub extern fn LLVMInitializeX86AsmParser() void;
extern fn ZigLLDLinkCOFF(argc: c_int, argv: [*:null]const ?[*:0]const u8, can_exit_early: bool) c_int;
extern fn ZigLLDLinkELF(argc: c_int, argv: [*:null]const ?[*:0]const u8, can_exit_early: bool) c_int;
diff --git a/src/codegen/riscv64.zig b/src/codegen/riscv64.zig
index 831f74b1b7..b297737816 100644
--- a/src/codegen/riscv64.zig
+++ b/src/codegen/riscv64.zig
@@ -390,7 +390,7 @@ pub const RawRegister = enum(u5) {
x24, x25, x26, x27, x28, x29, x30, x31,
pub fn dwarfLocOp(reg: RawRegister) u8 {
- return @enumToInt(reg) + DW.OP_reg0;
+ return @enumToInt(reg) + DW.OP.reg0;
}
};
@@ -424,7 +424,7 @@ pub const Register = enum(u5) {
}
pub fn dwarfLocOp(reg: Register) u8 {
- return @as(u8, @enumToInt(reg)) + DW.OP_reg0;
+ return @as(u8, @enumToInt(reg)) + DW.OP.reg0;
}
};
diff --git a/src/codegen/spirv/spec.zig b/src/codegen/spirv/spec.zig
index 429ed63d23..26d1925646 100644
--- a/src/codegen/spirv/spec.zig
+++ b/src/codegen/spirv/spec.zig
@@ -582,8 +582,8 @@ pub const Opcode = enum(u16) {
OpSpecConstantCompositeContinuedINTEL = 6092,
_,
- const OpReportIntersectionKHR = OpReportIntersectionNV;
- const OpTypeAccelerationStructureKHR = OpTypeAccelerationStructureNV;
+ const OpReportIntersectionKHR: Opcode = .OpReportIntersectionNV;
+ const OpTypeAccelerationStructureKHR: Opcode = .OpTypeAccelerationStructureNV;
};
pub const ImageOperands = packed struct {
Bias: bool align(@alignOf(u32)) = false,
diff --git a/src/codegen/x86.zig b/src/codegen/x86.zig
index fdad4e56db..5b981b9ef4 100644
--- a/src/codegen/x86.zig
+++ b/src/codegen/x86.zig
@@ -59,14 +59,14 @@ pub const Register = enum(u8) {
pub fn dwarfLocOp(reg: Register) u8 {
return switch (reg.to32()) {
- .eax => DW.OP_reg0,
- .ecx => DW.OP_reg1,
- .edx => DW.OP_reg2,
- .ebx => DW.OP_reg3,
- .esp => DW.OP_reg4,
- .ebp => DW.OP_reg5,
- .esi => DW.OP_reg6,
- .edi => DW.OP_reg7,
+ .eax => DW.OP.reg0,
+ .ecx => DW.OP.reg1,
+ .edx => DW.OP.reg2,
+ .ebx => DW.OP.reg3,
+ .esp => DW.OP.reg4,
+ .ebp => DW.OP.reg5,
+ .esi => DW.OP.reg6,
+ .edi => DW.OP.reg7,
else => unreachable,
};
}
diff --git a/src/codegen/x86_64.zig b/src/codegen/x86_64.zig
index 2964d7245e..72a7468041 100644
--- a/src/codegen/x86_64.zig
+++ b/src/codegen/x86_64.zig
@@ -115,23 +115,23 @@ pub const Register = enum(u8) {
pub fn dwarfLocOp(self: Register) u8 {
return switch (self.to64()) {
- .rax => DW.OP_reg0,
- .rdx => DW.OP_reg1,
- .rcx => DW.OP_reg2,
- .rbx => DW.OP_reg3,
- .rsi => DW.OP_reg4,
- .rdi => DW.OP_reg5,
- .rbp => DW.OP_reg6,
- .rsp => DW.OP_reg7,
-
- .r8 => DW.OP_reg8,
- .r9 => DW.OP_reg9,
- .r10 => DW.OP_reg10,
- .r11 => DW.OP_reg11,
- .r12 => DW.OP_reg12,
- .r13 => DW.OP_reg13,
- .r14 => DW.OP_reg14,
- .r15 => DW.OP_reg15,
+ .rax => DW.OP.reg0,
+ .rdx => DW.OP.reg1,
+ .rcx => DW.OP.reg2,
+ .rbx => DW.OP.reg3,
+ .rsi => DW.OP.reg4,
+ .rdi => DW.OP.reg5,
+ .rbp => DW.OP.reg6,
+ .rsp => DW.OP.reg7,
+
+ .r8 => DW.OP.reg8,
+ .r9 => DW.OP.reg9,
+ .r10 => DW.OP.reg10,
+ .r11 => DW.OP.reg11,
+ .r12 => DW.OP.reg12,
+ .r13 => DW.OP.reg13,
+ .r14 => DW.OP.reg14,
+ .r15 => DW.OP.reg15,
else => unreachable,
};
generated by cgit v1.2.3 (git 2.39.1) at 2025-12-28 08:27:00 +0000