6 files changed, 31 insertions, 31 deletions
diff --git a/src/codegen/aarch64.zig b/src/codegen/aarch64.zig
index 1c176df017..dfda04da85 100644
--- a/src/codegen/aarch64.zig
+++ b/src/codegen/aarch64.zig
@@ -52,7 +52,7 @@ pub const Register = enum(u6) {
     }
 
     pub fn dwarfLocOp(self: Register) u8 {
-        return @as(u8, self.id()) + DW.OP_reg0;
+        return @as(u8, self.id()) + DW.OP.reg0;
     }
 };
 
diff --git a/src/codegen/arm.zig b/src/codegen/arm.zig
index 42e3e52fac..ec9152f96b 100644
--- a/src/codegen/arm.zig
+++ b/src/codegen/arm.zig
@@ -170,7 +170,7 @@ pub const Register = enum(u5) {
     }
 
     pub fn dwarfLocOp(self: Register) u8 {
-        return @as(u8, self.id()) + DW.OP_reg0;
+        return @as(u8, self.id()) + DW.OP.reg0;
     }
 };
 
diff --git a/src/codegen/riscv64.zig b/src/codegen/riscv64.zig
index 831f74b1b7..b297737816 100644
--- a/src/codegen/riscv64.zig
+++ b/src/codegen/riscv64.zig
@@ -390,7 +390,7 @@ pub const RawRegister = enum(u5) {
     x24, x25, x26, x27, x28, x29, x30, x31,
 
     pub fn dwarfLocOp(reg: RawRegister) u8 {
-        return @enumToInt(reg) + DW.OP_reg0;
+        return @enumToInt(reg) + DW.OP.reg0;
     }
 };
 
@@ -424,7 +424,7 @@ pub const Register = enum(u5) {
     }
 
     pub fn dwarfLocOp(reg: Register) u8 {
-        return @as(u8, @enumToInt(reg)) + DW.OP_reg0;
+        return @as(u8, @enumToInt(reg)) + DW.OP.reg0;
     }
 };
 
diff --git a/src/codegen/spirv/spec.zig b/src/codegen/spirv/spec.zig
index 429ed63d23..26d1925646 100644
--- a/src/codegen/spirv/spec.zig
+++ b/src/codegen/spirv/spec.zig
@@ -582,8 +582,8 @@ pub const Opcode = enum(u16) {
     OpSpecConstantCompositeContinuedINTEL = 6092,
     _,
 
-    const OpReportIntersectionKHR = OpReportIntersectionNV;
-    const OpTypeAccelerationStructureKHR = OpTypeAccelerationStructureNV;
+    const OpReportIntersectionKHR: Opcode = .OpReportIntersectionNV;
+    const OpTypeAccelerationStructureKHR: Opcode = .OpTypeAccelerationStructureNV;
 };
 pub const ImageOperands = packed struct {
     Bias: bool align(@alignOf(u32)) = false,
diff --git a/src/codegen/x86.zig b/src/codegen/x86.zig
index fdad4e56db..5b981b9ef4 100644
--- a/src/codegen/x86.zig
+++ b/src/codegen/x86.zig
@@ -59,14 +59,14 @@ pub const Register = enum(u8) {
 
     pub fn dwarfLocOp(reg: Register) u8 {
         return switch (reg.to32()) {
-            .eax => DW.OP_reg0,
-            .ecx => DW.OP_reg1,
-            .edx => DW.OP_reg2,
-            .ebx => DW.OP_reg3,
-            .esp => DW.OP_reg4,
-            .ebp => DW.OP_reg5,
-            .esi => DW.OP_reg6,
-            .edi => DW.OP_reg7,
+            .eax => DW.OP.reg0,
+            .ecx => DW.OP.reg1,
+            .edx => DW.OP.reg2,
+            .ebx => DW.OP.reg3,
+            .esp => DW.OP.reg4,
+            .ebp => DW.OP.reg5,
+            .esi => DW.OP.reg6,
+            .edi => DW.OP.reg7,
             else => unreachable,
         };
     }
diff --git a/src/codegen/x86_64.zig b/src/codegen/x86_64.zig
index 2964d7245e..72a7468041 100644
--- a/src/codegen/x86_64.zig
+++ b/src/codegen/x86_64.zig
@@ -115,23 +115,23 @@ pub const Register = enum(u8) {
 
     pub fn dwarfLocOp(self: Register) u8 {
         return switch (self.to64()) {
-            .rax => DW.OP_reg0,
-            .rdx => DW.OP_reg1,
-            .rcx => DW.OP_reg2,
-            .rbx => DW.OP_reg3,
-            .rsi => DW.OP_reg4,
-            .rdi => DW.OP_reg5,
-            .rbp => DW.OP_reg6,
-            .rsp => DW.OP_reg7,
-
-            .r8 => DW.OP_reg8,
-            .r9 => DW.OP_reg9,
-            .r10 => DW.OP_reg10,
-            .r11 => DW.OP_reg11,
-            .r12 => DW.OP_reg12,
-            .r13 => DW.OP_reg13,
-            .r14 => DW.OP_reg14,
-            .r15 => DW.OP_reg15,
+            .rax => DW.OP.reg0,
+            .rdx => DW.OP.reg1,
+            .rcx => DW.OP.reg2,
+            .rbx => DW.OP.reg3,
+            .rsi => DW.OP.reg4,
+            .rdi => DW.OP.reg5,
+            .rbp => DW.OP.reg6,
+            .rsp => DW.OP.reg7,
+
+            .r8 => DW.OP.reg8,
+            .r9 => DW.OP.reg9,
+            .r10 => DW.OP.reg10,
+            .r11 => DW.OP.reg11,
+            .r12 => DW.OP.reg12,
+            .r13 => DW.OP.reg13,
+            .r14 => DW.OP.reg14,
+            .r15 => DW.OP.reg15,
 
             else => unreachable,
         };