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Diffstat (limited to 'src/codegen.zig')
-rw-r--r--src/codegen.zig101
1 files changed, 72 insertions, 29 deletions
diff --git a/src/codegen.zig b/src/codegen.zig
index a4f6f482b2..c60b6ee532 100644
--- a/src/codegen.zig
+++ b/src/codegen.zig
@@ -809,6 +809,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
.mul => try self.airMul(inst),
.mulwrap => try self.airMulWrap(inst),
.div => try self.airDiv(inst),
+ .rem => try self.airRem(inst),
.cmp_lt => try self.airCmp(inst, .lt),
.cmp_lte => try self.airCmp(inst, .lte),
@@ -898,7 +899,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
fn dbgSetPrologueEnd(self: *Self) InnerError!void {
switch (self.debug_output) {
.dwarf => |dbg_out| {
- try dbg_out.dbg_line.append(DW.LNS_set_prologue_end);
+ try dbg_out.dbg_line.append(DW.LNS.set_prologue_end);
try self.dbgAdvancePCAndLine(self.prev_di_line, self.prev_di_column);
},
.none => {},
@@ -908,7 +909,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
fn dbgSetEpilogueBegin(self: *Self) InnerError!void {
switch (self.debug_output) {
.dwarf => |dbg_out| {
- try dbg_out.dbg_line.append(DW.LNS_set_epilogue_begin);
+ try dbg_out.dbg_line.append(DW.LNS.set_epilogue_begin);
try self.dbgAdvancePCAndLine(self.prev_di_line, self.prev_di_column);
},
.none => {},
@@ -924,13 +925,13 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
// It lets you emit single-byte opcodes that add different numbers to
// both the PC and the line number at the same time.
try dbg_out.dbg_line.ensureUnusedCapacity(11);
- dbg_out.dbg_line.appendAssumeCapacity(DW.LNS_advance_pc);
+ dbg_out.dbg_line.appendAssumeCapacity(DW.LNS.advance_pc);
leb128.writeULEB128(dbg_out.dbg_line.writer(), delta_pc) catch unreachable;
if (delta_line != 0) {
- dbg_out.dbg_line.appendAssumeCapacity(DW.LNS_advance_line);
+ dbg_out.dbg_line.appendAssumeCapacity(DW.LNS.advance_line);
leb128.writeILEB128(dbg_out.dbg_line.writer(), delta_line) catch unreachable;
}
- dbg_out.dbg_line.appendAssumeCapacity(DW.LNS_copy);
+ dbg_out.dbg_line.appendAssumeCapacity(DW.LNS.copy);
},
.none => {},
}
@@ -1009,7 +1010,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
.dwarf => |dbg_out| {
assert(ty.hasCodeGenBits());
const index = dbg_out.dbg_info.items.len;
- try dbg_out.dbg_info.resize(index + 4); // DW.AT_type, DW.FORM_ref4
+ try dbg_out.dbg_info.resize(index + 4); // DW.AT.type, DW.FORM.ref4
const gop = try dbg_out.dbg_info_type_relocs.getOrPut(self.gpa, ty);
if (!gop.found_existing) {
@@ -1266,6 +1267,14 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
}
+ fn airRem(self: *Self, inst: Air.Inst.Index) !void {
+ const bin_op = self.air.instructions.items(.data)[inst].bin_op;
+ const result: MCValue = if (self.liveness.isUnused(inst)) .dead else switch (arch) {
+ else => return self.fail("TODO implement rem for {}", .{self.target.cpu.arch}),
+ };
+ return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
+ }
+
fn airBitAnd(self: *Self, inst: Air.Inst.Index) !void {
const bin_op = self.air.instructions.items(.data)[inst].bin_op;
const result: MCValue = if (self.liveness.isUnused(inst)) .dead else switch (arch) {
@@ -2429,13 +2438,13 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
.dwarf => |dbg_out| {
try dbg_out.dbg_info.ensureCapacity(dbg_out.dbg_info.items.len + 3);
dbg_out.dbg_info.appendAssumeCapacity(link.File.Elf.abbrev_parameter);
- dbg_out.dbg_info.appendSliceAssumeCapacity(&[2]u8{ // DW.AT_location, DW.FORM_exprloc
+ dbg_out.dbg_info.appendSliceAssumeCapacity(&[2]u8{ // DW.AT.location, DW.FORM.exprloc
1, // ULEB128 dwarf expression length
reg.dwarfLocOp(),
});
try dbg_out.dbg_info.ensureCapacity(dbg_out.dbg_info.items.len + 5 + name_with_null.len);
- try self.addDbgInfoTypeReloc(ty); // DW.AT_type, DW.FORM_ref4
- dbg_out.dbg_info.appendSliceAssumeCapacity(name_with_null); // DW.AT_name, DW.FORM_string
+ try self.addDbgInfoTypeReloc(ty); // DW.AT.type, DW.FORM.ref4
+ dbg_out.dbg_info.appendSliceAssumeCapacity(name_with_null); // DW.AT.name, DW.FORM.string
},
.none => {},
}
@@ -2458,15 +2467,15 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
var counting_writer = std.io.countingWriter(std.io.null_writer);
leb128.writeILEB128(counting_writer.writer(), adjusted_stack_offset) catch unreachable;
- // DW.AT_location, DW.FORM_exprloc
+ // DW.AT.location, DW.FORM.exprloc
// ULEB128 dwarf expression length
try leb128.writeULEB128(dbg_out.dbg_info.writer(), counting_writer.bytes_written + 1);
- try dbg_out.dbg_info.append(DW.OP_breg11);
+ try dbg_out.dbg_info.append(DW.OP.breg11);
try leb128.writeILEB128(dbg_out.dbg_info.writer(), adjusted_stack_offset);
try dbg_out.dbg_info.ensureCapacity(dbg_out.dbg_info.items.len + 5 + name_with_null.len);
- try self.addDbgInfoTypeReloc(ty); // DW.AT_type, DW.FORM_ref4
- dbg_out.dbg_info.appendSliceAssumeCapacity(name_with_null); // DW.AT_name, DW.FORM_string
+ try self.addDbgInfoTypeReloc(ty); // DW.AT.type, DW.FORM.ref4
+ dbg_out.dbg_info.appendSliceAssumeCapacity(name_with_null); // DW.AT.name, DW.FORM.string
},
else => {},
}
@@ -5182,25 +5191,59 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
return error.CodegenFail;
}
- usingnamespace switch (arch) {
- .i386 => @import("codegen/x86.zig"),
- .x86_64 => @import("codegen/x86_64.zig"),
- .riscv64 => @import("codegen/riscv64.zig"),
- .arm, .armeb => @import("codegen/arm.zig"),
- .aarch64, .aarch64_be, .aarch64_32 => @import("codegen/aarch64.zig"),
- else => struct {
- pub const Register = enum {
- dummy,
-
- pub fn allocIndex(self: Register) ?u4 {
- _ = self;
- return null;
- }
- };
- pub const callee_preserved_regs = [_]Register{};
+ const Register = switch (arch) {
+ .i386 => @import("codegen/x86.zig").Register,
+ .x86_64 => @import("codegen/x86_64.zig").Register,
+ .riscv64 => @import("codegen/riscv64.zig").Register,
+ .arm, .armeb => @import("codegen/arm.zig").Register,
+ .aarch64, .aarch64_be, .aarch64_32 => @import("codegen/aarch64.zig").Register,
+ else => enum {
+ dummy,
+
+ pub fn allocIndex(self: Register) ?u4 {
+ _ = self;
+ return null;
+ }
},
};
+ const Instruction = switch (arch) {
+ .riscv64 => @import("codegen/riscv64.zig").Instruction,
+ .arm, .armeb => @import("codegen/arm.zig").Instruction,
+ .aarch64, .aarch64_be, .aarch64_32 => @import("codegen/aarch64.zig").Instruction,
+ else => void,
+ };
+
+ const Condition = switch (arch) {
+ .arm, .armeb => @import("codegen/arm.zig").Condition,
+ else => void,
+ };
+
+ const callee_preserved_regs = switch (arch) {
+ .i386 => @import("codegen/x86.zig").callee_preserved_regs,
+ .x86_64 => @import("codegen/x86_64.zig").callee_preserved_regs,
+ .riscv64 => @import("codegen/riscv64.zig").callee_preserved_regs,
+ .arm, .armeb => @import("codegen/arm.zig").callee_preserved_regs,
+ .aarch64, .aarch64_be, .aarch64_32 => @import("codegen/aarch64.zig").callee_preserved_regs,
+ else => [_]Register{},
+ };
+
+ const c_abi_int_param_regs = switch (arch) {
+ .i386 => @import("codegen/x86.zig").c_abi_int_param_regs,
+ .x86_64 => @import("codegen/x86_64.zig").c_abi_int_param_regs,
+ .arm, .armeb => @import("codegen/arm.zig").c_abi_int_param_regs,
+ .aarch64, .aarch64_be, .aarch64_32 => @import("codegen/aarch64.zig").c_abi_int_param_regs,
+ else => [_]Register{},
+ };
+
+ const c_abi_int_return_regs = switch (arch) {
+ .i386 => @import("codegen/x86.zig").c_abi_int_return_regs,
+ .x86_64 => @import("codegen/x86_64.zig").c_abi_int_return_regs,
+ .arm, .armeb => @import("codegen/arm.zig").c_abi_int_return_regs,
+ .aarch64, .aarch64_be, .aarch64_32 => @import("codegen/aarch64.zig").c_abi_int_return_regs,
+ else => [_]Register{},
+ };
+
fn parseRegName(name: []const u8) ?Register {
if (@hasDecl(Register, "parseRegName")) {
return Register.parseRegName(name);
generated by cgit v1.2.3 (git 2.39.1) at 2025-12-28 05:59:51 +0000