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| author | Andrew Kelley <andrew@ziglang.org> | 2024-10-17 12:54:44 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-10-17 12:54:44 -0700 |
| commit | 8504e1f550ba697f29fd72f181d9009ebad09501 (patch) | |
| tree | 1a90c3da1ff4afdb23dc5415370874efe5778f23 /test/tests.zig | |
| parent | 816dfca0b579440604eb871c6a76a3edd250240f (diff) | |
| parent | 6302a90cbf9978766757e11808e7764d5c4611b1 (diff) | |
| download | zig-8504e1f550ba697f29fd72f181d9009ebad09501.tar.gz zig-8504e1f550ba697f29fd72f181d9009ebad09501.zip | |
Merge pull request #21610 from alexrp/riscv-abis
Fix some RISC-V ABI issues and add ILP32/LP64 (soft float) to module tests
Diffstat (limited to 'test/tests.zig')
| -rw-r--r-- | test/tests.zig | 30 |
1 files changed, 29 insertions, 1 deletions
diff --git a/test/tests.zig b/test/tests.zig index 017f9478a9..a9035560b3 100644 --- a/test/tests.zig +++ b/test/tests.zig @@ -580,6 +580,20 @@ const test_targets = blk: { }, .{ + .target = std.Target.Query.parse(.{ + .arch_os_abi = "riscv32-linux-none", + .cpu_features = "baseline-d-f", + }) catch unreachable, + }, + .{ + .target = std.Target.Query.parse(.{ + .arch_os_abi = "riscv32-linux-musl", + .cpu_features = "baseline-d-f", + }) catch unreachable, + .link_libc = true, + }, + + .{ .target = .{ .cpu_arch = .riscv32, .os_tag = .linux, @@ -604,6 +618,20 @@ const test_targets = blk: { }, .{ + .target = std.Target.Query.parse(.{ + .arch_os_abi = "riscv64-linux-none", + .cpu_features = "baseline-d-f", + }) catch unreachable, + }, + .{ + .target = std.Target.Query.parse(.{ + .arch_os_abi = "riscv64-linux-musl", + .cpu_features = "baseline-d-f", + }) catch unreachable, + .link_libc = true, + }, + + .{ .target = .{ .cpu_arch = .riscv64, .os_tag = .linux, @@ -631,7 +659,7 @@ const test_targets = blk: { .target = std.Target.Query.parse(.{ .arch_os_abi = "riscv64-linux-musl", .cpu_features = "baseline+v+zbb", - }) catch @panic("OOM"), + }) catch unreachable, .use_llvm = false, .use_lld = false, }, |