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authorAndrew Kelley <andrew@ziglang.org>2020-07-20 13:11:07 -0700
committerAndrew Kelley <andrew@ziglang.org>2020-07-20 13:12:20 -0700
commitef91b11295a549a8173c488d9fd5b3f69b419829 (patch)
tree4b2ef95d5e1dba821b77bfdc4f5e25db127249cc /test/stage2
parenta8065a05a5bc3df4036f1d7abe0928901cf7f5df (diff)
downloadzig-ef91b11295a549a8173c488d9fd5b3f69b419829.tar.gz
zig-ef91b11295a549a8173c488d9fd5b3f69b419829.zip
stage2: register allocator processes operand deaths
also rework the IR data structures
Diffstat (limited to 'test/stage2')
-rw-r--r--test/stage2/compare_output.zig37
1 files changed, 37 insertions, 0 deletions
diff --git a/test/stage2/compare_output.zig b/test/stage2/compare_output.zig
index 6a6772f935..d013573e30 100644
--- a/test/stage2/compare_output.zig
+++ b/test/stage2/compare_output.zig
@@ -267,5 +267,42 @@ pub fn addCases(ctx: *TestContext) !void {
,
"",
);
+
+ // Requires a second move. The register allocator should figure out to re-use rax.
+ case.addCompareOutput(
+ \\export fn _start() noreturn {
+ \\ add(3, 4);
+ \\
+ \\ exit();
+ \\}
+ \\
+ \\fn add(a: u32, b: u32) void {
+ \\ const c = a + b; // 7
+ \\ const d = a + c; // 10
+ \\ const e = d + b; // 14
+ \\ const f = d + e; // 24
+ \\ const g = e + f; // 38
+ \\ const h = f + g; // 62
+ \\ const i = g + h; // 100
+ \\ const j = i + d; // 110
+ \\ assert(j == 110);
+ \\}
+ \\
+ \\pub fn assert(ok: bool) void {
+ \\ if (!ok) unreachable; // assertion failure
+ \\}
+ \\
+ \\fn exit() noreturn {
+ \\ asm volatile ("syscall"
+ \\ :
+ \\ : [number] "{rax}" (231),
+ \\ [arg1] "{rdi}" (0)
+ \\ : "rcx", "r11", "memory"
+ \\ );
+ \\ unreachable;
+ \\}
+ ,
+ "",
+ );
}
}