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| author | Alex Rønne Petersen <alex@alexrp.com> | 2025-04-07 17:23:32 +0200 |
|---|---|---|
| committer | Alex Rønne Petersen <alex@alexrp.com> | 2025-04-11 02:28:35 +0200 |
| commit | 382aa48f044ff87d50e1c185a12173be562275f2 (patch) | |
| tree | d5b0f111b85b9983d353adf98bb8d36092992876 /test/behavior/floatop.zig | |
| parent | 0a5c088ecc2fbe4db5cae1cc5cf62eeba340375d (diff) | |
| download | zig-382aa48f044ff87d50e1c185a12173be562275f2.tar.gz zig-382aa48f044ff87d50e1c185a12173be562275f2.zip | |
test: Disable a bunch of vector behavior tests for hexagon.
Most of the failures are:
* https://github.com/llvm/llvm-project/issues/118879
* https://github.com/llvm/llvm-project/issues/134659
But some are also miscompilations leading to wrong results. I'm not going to
investigate the latter further until all the backend crashes have been resolved.
Diffstat (limited to 'test/behavior/floatop.zig')
| -rw-r--r-- | test/behavior/floatop.zig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/test/behavior/floatop.zig b/test/behavior/floatop.zig index 77fa4c593f..61a7258901 100644 --- a/test/behavior/floatop.zig +++ b/test/behavior/floatop.zig @@ -241,6 +241,7 @@ test "vector cmp f16" { if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest; if (builtin.cpu.arch.isArm()) return error.SkipZigTest; if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest; + if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest; try testCmpVector(f16); try comptime testCmpVector(f16); @@ -254,6 +255,7 @@ test "vector cmp f32" { if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest; if (builtin.cpu.arch.isArm()) return error.SkipZigTest; if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest; + if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest; try testCmpVector(f32); try comptime testCmpVector(f32); @@ -266,6 +268,7 @@ test "vector cmp f64" { if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest; if (builtin.cpu.arch.isArm()) return error.SkipZigTest; if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest; + if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest; try testCmpVector(f64); try comptime testCmpVector(f64); @@ -281,6 +284,7 @@ test "vector cmp f128" { if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest; if (builtin.cpu.arch.isArm()) return error.SkipZigTest; if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest; + if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest; try testCmpVector(f128); try comptime testCmpVector(f128); |