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| author | Andrew Kelley <andrew@ziglang.org> | 2019-07-18 15:03:21 -0400 |
|---|---|---|
| committer | Andrew Kelley <andrew@ziglang.org> | 2019-07-18 15:03:21 -0400 |
| commit | a3854d042e0d05a87ae9f0b71d12474c8d0e57ec (patch) | |
| tree | 7f0a97f024aea3eb3d1f6775acd9439075aebe0f /std/os/bits/linux.zig | |
| parent | 07f0de6a8a9a152cfbd76e458d99d992b59e9e06 (diff) | |
| download | zig-a3854d042e0d05a87ae9f0b71d12474c8d0e57ec.tar.gz zig-a3854d042e0d05a87ae9f0b71d12474c8d0e57ec.zip | |
basic riscv support
llvm is giving me `error: couldn't allocate output register for
constraint '{a0}'` which is a bug that needs to be fixed upstream.
Diffstat (limited to 'std/os/bits/linux.zig')
| -rw-r--r-- | std/os/bits/linux.zig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/std/os/bits/linux.zig b/std/os/bits/linux.zig index 8430a05bf0..d7c23ffadb 100644 --- a/std/os/bits/linux.zig +++ b/std/os/bits/linux.zig @@ -7,6 +7,7 @@ pub usingnamespace @import("linux/errno.zig"); pub usingnamespace switch (builtin.arch) { .x86_64 => @import("linux/x86_64.zig"), .aarch64 => @import("linux/arm64.zig"), + .riscv64 => @import("linux/riscv64.zig"), else => struct {}, }; |