riscv: add stage2_riscv to test matrix and bypass failing tests

4 files changed, 51 insertions, 15 deletions

diff --git a/src/arch/riscv64/CodeGen.zig b/src/arch/riscv64/CodeGen.zig
index f36613473b..d9f31b4a14 100644
--- a/src/arch/riscv64/CodeGen.zig
+++ b/src/arch/riscv64/CodeGen.zig
@@ -1448,9 +1448,15 @@ fn computeFrameLayout(self: *Self) !FrameLayout {
     // The total frame size is calculated by the amount of s registers you need to save * 8, as each
     // register is 8 bytes, the total allocation sizes, and 16 more register for the spilled ra and s0
     // register. Finally we align the frame size to the align of the base pointer.
+    const args_frame_size = frame_size[@intFromEnum(FrameIndex.args_frame)];
+    const spill_frame_size = frame_size[@intFromEnum(FrameIndex.spill_frame)];
+    const call_frame_size = frame_size[@intFromEnum(FrameIndex.call_frame)];
+
+    // TODO: this 24 should be a 16, but we were clobbering the top and bottom of the frame.
+    // maybe everything can go from the bottom?
     const acc_frame_size: i32 = std.mem.alignForward(
         i32,
-        total_alloc_size + 16 + frame_size[@intFromEnum(FrameIndex.args_frame)] + frame_size[@intFromEnum(FrameIndex.spill_frame)],
+        total_alloc_size + 64 + args_frame_size + spill_frame_size + call_frame_size,
         @intCast(frame_align[@intFromEnum(FrameIndex.base_ptr)].toByteUnits().?),
     );
     log.debug("frame size: {}", .{acc_frame_size});
@@ -1771,8 +1777,8 @@ fn airNot(self: *Self, inst: Air.Inst.Index) !void {
                     try self.register_manager.allocReg(inst, gp);
 
                 _ = try self.addInst(.{
-                    .tag = .not,
-                    .ops = .rr,
+                    .tag = .pseudo,
+                    .ops = .pseudo_not,
                     .data = .{
                         .rr = .{
                             .rs = operand_reg,
@@ -1870,7 +1876,7 @@ fn binOp(
                         return self.fail("TODO binary operations on int with bits > 64", .{});
                     }
                 },
-                else => |x| return std.debug.panic("TOOD: binOp {s}", .{@tagName(x)}),
+                else => |x| return self.fail("TOOD: binOp {s}", .{@tagName(x)}),
             }
         },
 
@@ -1988,6 +1994,7 @@ fn binOpRegister(
         .cmp_gt,
         .cmp_gte,
         .cmp_lt,
+        .cmp_lte,
         => .pseudo,
 
         else => return self.fail("TODO: binOpRegister {s}", .{@tagName(tag)}),
@@ -2020,6 +2027,7 @@ fn binOpRegister(
                 .cmp_gt,
                 .cmp_gte,
                 .cmp_lt,
+                .cmp_lte,
                 => .pseudo_compare,
                 else => unreachable,
             };
@@ -2773,10 +2781,11 @@ fn airArrayElemVal(self: *Self, inst: Air.Inst.Index) !void {
         const dst_mcv = try self.allocRegOrMem(inst, false);
         _ = try self.addInst(.{
             .tag = .add,
-            .ops = .rr,
-            .data = .{ .rr = .{
+            .ops = .rrr,
+            .data = .{ .r_type = .{
                 .rd = addr_reg,
-                .rs = offset_reg,
+                .rs1 = offset_reg,
+                .rs2 = addr_reg,
             } },
         });
         try self.genCopy(elem_ty, dst_mcv, .{ .indirect = .{ .reg = addr_reg } });
@@ -3723,7 +3732,7 @@ fn genVarDbgInfo(
                 .undef => .undef,
                 .none => .none,
                 else => blk: {
-                    log.warn("TODO generate debug info for {}", .{mcv});
+                    // log.warn("TODO generate debug info for {}", .{mcv});
                     break :blk .nop;
                 },
             };
@@ -4289,7 +4298,7 @@ fn genCopy(self: *Self, ty: Type, dst_mcv: MCValue, src_mcv: MCValue) !void {
 
     if (!dst_mcv.isMutable()) {
         // panic so we can see the trace
-        return std.debug.panic("tried to genCopy immutable: {s}", .{@tagName(dst_mcv)});
+        return self.fail("tried to genCopy immutable: {s}", .{@tagName(dst_mcv)});
     }
 
     switch (dst_mcv) {
@@ -4344,7 +4353,7 @@ fn genCopy(self: *Self, ty: Type, dst_mcv: MCValue, src_mcv: MCValue) !void {
                 part_disp += @intCast(dst_ty.abiSize(zcu));
             }
         },
-        else => return std.debug.panic("TODO: genCopy {s} with {s}", .{ @tagName(dst_mcv), @tagName(src_mcv) }),
+        else => return self.fail("TODO: genCopy to {s} from {s}", .{ @tagName(dst_mcv), @tagName(src_mcv) }),
     }
 }
 
diff --git a/src/arch/riscv64/Encoding.zig b/src/arch/riscv64/Encoding.zig
index d145e21603..c23ba10d9b 100644
--- a/src/arch/riscv64/Encoding.zig
+++ b/src/arch/riscv64/Encoding.zig
@@ -14,6 +14,8 @@ pub const Mnemonic = enum {
     sltu,
     xori,
     andi,
+    slli,
+    srli,
 
     addi,
     jalr,
@@ -35,6 +37,7 @@ pub const Mnemonic = enum {
 
     // R Type
     add,
+    sub,
     slt,
     mul,
     xor,
@@ -48,6 +51,7 @@ pub const Mnemonic = enum {
         return switch (mnem) {
             // zig fmt: off
             .add    => .{ .opcode = 0b0110011, .funct3 = 0b000, .funct7 = 0b0000000 },
+            .sub    => .{ .opcode = 0b0110011, .funct3 = 0b000, .funct7 = 0b0100000 }, 
 
             .ld     => .{ .opcode = 0b0000011, .funct3 = 0b011, .funct7 = null      },
             .lw     => .{ .opcode = 0b0000011, .funct3 = 0b010, .funct7 = null      },
@@ -63,6 +67,8 @@ pub const Mnemonic = enum {
             .andi   => .{ .opcode = 0b0010011, .funct3 = 0b111, .funct7 = null      },
             .xori   => .{ .opcode = 0b0010011, .funct3 = 0b100, .funct7 = null      },
             .jalr   => .{ .opcode = 0b1100111, .funct3 = 0b000, .funct7 = null      },
+            .slli   => .{ .opcode = 0b0010011, .funct3 = 0b001, .funct7 = null      },
+            .srli   => .{ .opcode = 0b0010011, .funct3 = 0b101, .funct7 = null      },
 
             .lui    => .{ .opcode = 0b0110111, .funct3 = null,  .funct7 = null      },
 
@@ -103,9 +109,6 @@ pub const InstEnc = enum {
 
     pub fn fromMnemonic(mnem: Mnemonic) InstEnc {
         return switch (mnem) {
-            .add,
-            => .R,
-
             .addi,
             .ld,
             .lw,
@@ -118,6 +121,8 @@ pub const InstEnc = enum {
             .sltiu,
             .xori,
             .andi,
+            .slli,
+            .srli,
             => .I,
 
             .lui,
@@ -139,6 +144,8 @@ pub const InstEnc = enum {
             .sltu,
             .mul,
             .xor,
+            .add,
+            .sub,
             => .R,
 
             .ecall,
diff --git a/src/arch/riscv64/Lower.zig b/src/arch/riscv64/Lower.zig
index 41bb5c6599..4b77f9cdee 100644
--- a/src/arch/riscv64/Lower.zig
+++ b/src/arch/riscv64/Lower.zig
@@ -221,7 +221,19 @@ pub fn lowerMir(lower: *Lower, index: Mir.Inst.Index) Error!struct {
                             .{ .reg = rs2 },
                         });
                     },
-                    else => return lower.fail("TODO lower: pseudo_compare {s}", .{@tagName(op)}),
+                    .lte => {
+                        try lower.emit(.slt, &.{
+                            .{ .reg = rd },
+                            .{ .reg = rs2 },
+                            .{ .reg = rs1 },
+                        });
+
+                        try lower.emit(.xori, &.{
+                            .{ .reg = rd },
+                            .{ .reg = rd },
+                            .{ .imm = Immediate.s(1) },
+                        });
+                    },
                 }
             },
 
@@ -258,6 +270,10 @@ fn generic(lower: *Lower, inst: Mir.Inst) Error!void {
             .{ .reg = inst.data.u_type.rd },
             .{ .imm = inst.data.u_type.imm20 },
         },
+        .rr => &.{
+            .{ .reg = inst.data.rr.rd },
+            .{ .reg = inst.data.rr.rs },
+        },
         .rri => &.{
             .{ .reg = inst.data.i_type.rd },
             .{ .reg = inst.data.i_type.rs1 },
@@ -293,7 +309,7 @@ fn reloc(lower: *Lower, target: Reloc.Target) Immediate {
 }
 
 fn pushPopRegList(lower: *Lower, comptime spilling: bool, reg_list: Mir.RegisterList) !void {
-    var it = reg_list.iterator(.{ .direction = if (spilling) .forward else .reverse });
+    var it = reg_list.iterator(.{ .direction = .forward });
 
     var reg_i: u31 = 0;
     while (it.next()) |i| {
diff --git a/src/arch/riscv64/abi.zig b/src/arch/riscv64/abi.zig
index 98de968142..468fede917 100644
--- a/src/arch/riscv64/abi.zig
+++ b/src/arch/riscv64/abi.zig
@@ -96,6 +96,10 @@ pub fn classifyType(ty: Type, mod: *Module) Class {
 pub fn classifySystem(ty: Type, mod: *Module) [8]Class {
     var result = [1]Class{.none} ** 8;
     switch (ty.zigTypeTag(mod)) {
+        .Bool, .Void, .NoReturn => {
+            result[0] = .integer;
+            return result;
+        },
         .Pointer => switch (ty.ptrSize(mod)) {
             .Slice => {
                 result[0] = .integer;