diff options
| author | joachimschmidt557 <joachim.schmidt557@outlook.com> | 2022-02-12 21:12:18 +0100 |
|---|---|---|
| committer | joachimschmidt557 <joachim.schmidt557@outlook.com> | 2022-02-14 22:09:44 +0100 |
| commit | 783e216e7d49ce30032cd768ca266f5f08773bf4 (patch) | |
| tree | 13bc364a2fec50885949698da74ebc83241d21af /src | |
| parent | 1c37622659f70115b698b5924472c2268bca63a8 (diff) | |
| download | zig-783e216e7d49ce30032cd768ca266f5f08773bf4.tar.gz zig-783e216e7d49ce30032cd768ca266f5f08773bf4.zip | |
stage2 AArch64: Fix issue in binOp and add regression test
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/aarch64/CodeGen.zig | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/src/arch/aarch64/CodeGen.zig b/src/arch/aarch64/CodeGen.zig index 8bd5324ed1..8b5503f293 100644 --- a/src/arch/aarch64/CodeGen.zig +++ b/src/arch/aarch64/CodeGen.zig @@ -981,13 +981,19 @@ fn binOpRegister( if (lhs_is_register) self.register_manager.freezeRegs(&.{lhs.register}); if (rhs_is_register) self.register_manager.freezeRegs(&.{rhs.register}); + const branch = &self.branch_stack.items[self.branch_stack.items.len - 1]; + const lhs_reg = if (lhs_is_register) lhs.register else blk: { const track_inst: ?Air.Inst.Index = if (maybe_inst) |inst| inst: { const bin_op = self.air.instructions.items(.data)[inst].bin_op; break :inst Air.refToIndex(bin_op.lhs).?; } else null; + const reg = try self.register_manager.allocReg(track_inst); self.register_manager.freezeRegs(&.{reg}); + + if (track_inst) |inst| branch.inst_table.putAssumeCapacity(inst, .{ .register = reg }); + break :blk reg; }; defer self.register_manager.unfreezeRegs(&.{lhs_reg}); @@ -997,8 +1003,12 @@ fn binOpRegister( const bin_op = self.air.instructions.items(.data)[inst].bin_op; break :inst Air.refToIndex(bin_op.rhs).?; } else null; + const reg = try self.register_manager.allocReg(track_inst); self.register_manager.freezeRegs(&.{reg}); + + if (track_inst) |inst| branch.inst_table.putAssumeCapacity(inst, .{ .register = reg }); + break :blk reg; }; defer self.register_manager.unfreezeRegs(&.{rhs_reg}); @@ -1077,6 +1087,8 @@ fn binOpImmediate( if (lhs_is_register) self.register_manager.freezeRegs(&.{lhs.register}); + const branch = &self.branch_stack.items[self.branch_stack.items.len - 1]; + const lhs_reg = if (lhs_is_register) lhs.register else blk: { const track_inst: ?Air.Inst.Index = if (maybe_inst) |inst| inst: { const bin_op = self.air.instructions.items(.data)[inst].bin_op; @@ -1084,8 +1096,12 @@ fn binOpImmediate( if (lhs_and_rhs_swapped) bin_op.rhs else bin_op.lhs, ).?; } else null; + const reg = try self.register_manager.allocReg(track_inst); self.register_manager.freezeRegs(&.{reg}); + + if (track_inst) |inst| branch.inst_table.putAssumeCapacity(inst, .{ .register = reg }); + break :blk reg; }; defer self.register_manager.unfreezeRegs(&.{lhs_reg}); @@ -3141,7 +3157,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void .tag = .cset, .data = .{ .r_cond = .{ .rd = reg, - .cond = condition, + .cond = condition.negate(), } }, }); }, |